6

NR102405

HV2701

Logic Function Table

INPUT DATA

OUTPUT SWITCH

LATCH

ENABLE CLOCK

Notes:

1.

Th 16 switches operate independently.

2.

Serial data is clocked in on the L to H transition of the CLK.

3.

All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch.

4.

D

5.

Shift registers clocking has no effect on the switch states if LE is high.

6.

The CL clear input overrides all other inputs.

Logic Timing Waveforms

DATA

IN

LE

CLOCK

DATA

OUT

OFF

ON

OUT

(TYP )

V

50%

50%

50%

50%

t

SD

t

SU

t

h

50%

50%

50%

CLR

D

N– 1

D

N

D

N+ 1

50%

50%

90%

10%