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RM48L940 Fiches technique(PDF) 56 Page - Texas Instruments

No de pièce RM48L940
Description  RM48Lx40 16- and 32-Bit RISC Flash Microcontroller
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

RM48L940 Fiches technique(HTML) 56 Page - Texas Instruments

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RM48L940, RM48L740, RM48L540
SPNS175C – APRIL 2012 – REVISED JUNE 2015
www.ti.com
6.5
ARM Cortex-R4F CPU Information
6.5.1
Summary of ARM Cortex-R4F CPU Features
The features of the ARM Cortex-R4F CPU include:
An integer unit with integral EmbeddedICE-RT logic.
High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
Floating Point Coprocessor
Dynamic branch prediction with a global history buffer, and a 4-entry return stack
Low interrupt latency.
Nonmaskable interrupt.
A Harvard Level one (L1) memory system with:
Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
Dual core logic for fault detection in safety-critical applications.
An L2 memory interface:
Single 64-bit master AXI interface
64-bit slave AXI interface to TCM RAM blocks
A debug interface to a CoreSight Debug Access Port (DAP).
Six Hardware Breakpoints
Two Watchpoints
A trace interface to a CoreSight ETM-R4.
A Performance Monitoring Unit (PMU).
A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F CPU see www.arm.com.
6.5.2
ARM Cortex-R4F CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
ECC On TCM Accesses
Hardware VIC Port
Floating Point Coprocessor
MPU
6.5.3
Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-
R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two
clock cycles as shown in Figure 6-3.
The CPUs have a diverse CPU placement given by following requirements:
different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
dedicated guard ring for each CPU
56
System Information and Electrical Specifications
Copyright © 2012–2015, Texas Instruments Incorporated
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