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LMR50410-Q1 Fiches technique(PDF) 20 Page - Texas Instruments

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No de pièce LMR50410-Q1
Description  LMR50410-Q1 SIMPLE SWITCHER짰 4-V to 36-V, 1-A Buck Converter in SOT-23-6 package
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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9.2.2.6 Input Capacitor Selection
The LMR50410-Q1 device requires a high frequency input decoupling capacitor or capacitor. The typical
recommended value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type
X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than the
maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the
maximum input voltage is recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is
used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the
current rating is 1 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close
as possible to the device pins.
9.2.2.7 Bootstrap Capacitor
Every LMR50410-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is
0.1 µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.8 Undervoltage Lockout Set-Point
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. Equation 13 can be used to determine the VIN UVLO level.
ENT
ENB
IN_RISING
ENH
ENB
R
+ R
V
= V
×
R
(13)
The EN rising threshold (VENH) for LMR50410-Q1 is set to be 1.23 V (typical). Choose a value of 200 kΩ for
RENB to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT
can be calculated using Equation 14:
IN_RISING
ENT
ENB
ENH
V
R
=
- 1 × R
V
§
·
¨
¸
¨
¸
©
¹
(14)
The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling
UVLO threshold, equals 5.3 V, can be calculated by Equation 15 where EN hysteresis voltage, VEN_HYS, is 0.13
V (typical).
ENT
ENB
IN_FALLING
ENH
EN_HYS
ENB
R
+ R
V
= V
- V
×
R
(15)
9.2.2.9 Maximum Ambient Temperature
As with any power conversion device, the LMR50410-Q1 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum internal die temperature for the LMR50410-Q1 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. Equation 16 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC
Package Thermal Metrics Application Report, the value of RθJA given in Section 7.4 is not valid for design
purposes and must not be used to estimate the thermal performance of the application. The values reported in
that table were measured under a specific set of conditions that are rarely obtained in an actual application.
LMR50410-Q1
SLUSDW4 – JULY 2020
www.ti.com
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