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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AWR2243 Fiches technique(PDF) 34 Page - Texas Instruments |
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AWR2243 Fiches technique(HTML) 34 Page - Texas Instruments |
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34 / 62 page  8.9.8 Camera Serial Interface (CSI) The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity of each wire of a lane is also configurable. Section 8.9.8.1, Figure 8-10, Figure 8-11, and Figure 8-12 describe the clock and data timing of the CSI.The clock is always ON once the CSI IP is enabled. Hence it remains in HS mode. 8.9.8.1 CSI Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT HPTX HSTXDBR Data bit rate (1/2/4 data lane PHY) 150 600 Mbps fCLK DDR clock frequency (1/2/4 data lane PHY) 75 300 MHz ΔVCMTX(LF) Common-level variation –50 50 mV tR and tF 20% to 80% rise time and fall time 0.3 UI LPTX DRIVER tEOT Time from start of THS-TRAIL period to start of LP-11 state 105 + 12*UI ns DATA-CLOCK Timing Specification UINOM Nominal Unit Interval 1.67 13.33 ns UIINST,MIN Minimum instantaneous Unit Interval 1.131 ns TSKEW[TX] Data to clock skew measured at transmitter –0.15 0.15 UIINST, MIN CSI2 TIMING SPECIFICATION TCLK-PRE Time that the HS clock shall be driven by the transmitter before any associated data lane beginning the transition from LP to HS mode. 8 ns TCLK-PREPARE Time that the transmitter drives the clock lane LP-00 line state immediately before the HS-0 line state starting the HS transmission. 38 95 ns TCLK-PREPARE + TCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state before starting the clock. 300 ns TEOT Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL, to the start of the LP-11 state following a HS burst. 105 ns + 12*UI ns THS-PREPARE Time that the transmitter drives the data lane LP-00 line state immediately before the HS-0 line state starting the HS transmission 40 + 4*UI 85 + 6*UI ns THS-PREPARE + THS-ZERO THS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI ns THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns THS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst max(8*UI, 60 ns + 4*UI) ns TLPX TXXXransmitted length of any low-power state period 50 ns CSI2_CLK(P/M) CSI2_TX(P/M) 1 UI 0.5UI + Tskew Figure 8-10. Clock and Data Timing in HS Transmission AWR2243 SWRS223A – FEBRUARY 2020 – REVISED AUGUST 2020 www.ti.com 34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: AWR2243 |
Numéro de pièce similaire - AWR2243_V01 |
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Description similaire - AWR2243_V01 |
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