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AM29DL642G70I Fiches technique(PDF) 11 Page - Advanced Micro Devices |
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AM29DL642G70I Fiches technique(HTML) 11 Page - Advanced Micro Devices |
11 / 54 page June 10, 2005 Am29DL642G 9 PRELIMINARY DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29DL642G Device Bus Operations Legend: L = Logic Low = V IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, A IN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 3. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at the same time. 4. If WP#/ACC = V IL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V HH, all sectors will be unprotected. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the ac- tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# (or CE2#) to VIL, and OE# to VIH. Operation CE# (Note 3) OE# WE# RESET# WP#/ACC Addresses (Note 1) DQ15– DQ0 Read L L H H L/H A IN D OUT Write L H L H (Note 4) A IN D IN Standby V CC ± 0.3 V XX V CC ± 0.3 V L/H X High-Z Output Disable L H H H L/H X High-Z Reset X X X L L/H X High-Z Sector Protect (Note 2) L H L V ID L/H SA, A6 = L, A1 = H, A0 = L D IN Sector Unprotect (Note 2) L H L V ID (Note 4) SA, A6 = H, A1 = H, A0 = L D IN Temporary Sector Unprotect X X X V ID (Note 4) A IN D IN |
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