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NBLVEP16VR Fiches technique(PDF) 4 Page - ON Semiconductor

No de pièce NBLVEP16VR
Description  2.5V/3.3V/5V ECL Differential Receiver/Driver with Oscillator Gain Stage and Enabled High Gain Outputs
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The NBLVEP16VR is an ECL/LVPECL oscillator gain
stage with high−gain output buffers, selectable output
enable and a feedback buffer. The NBLVEP16VR is a
enhanced with EN, a synchronous output enable pin to
eliminate runt pulses; EN_SEL, an input state selector pin
offering LVCMOS/LVTTL or ECL/LVPECL level control
of EN; and OD_MODE, an output disable mode state pin
which selects the polarity of the high−gain output’s disabled
The NBLVEP16VR Q and Q outputs are ideal for
feedback applications common in crystal oscillator gain
blocks. They each have a selectable on−chip pull−down
current source. External resistors may be used to increase the
pull−down current to a maximum of 25 mA. The QHG and
QHG outputs each have an optional on−chip pull−down
current source of 10 mA. When VEEP is left open, the 10 mA
output current sources are disabled and the QHG and QHG
outputs operate as standard ECL/LVPECL. When VEEP is
connected to VEE, the 10 mA current sources are activated.
The QHG and QHG pull−down current can be decreased by
using a resistor connect from VEEP to VEE. See current
source truth table for functions and options.
The output enable input pin, EN, is synchronized with the
D and D data input signals in a way that furnishes glitchless
gating of the QHG and QHG outputs and allows continuous
oscillator operation. For applications that require output
enable control, the NBLVEP16VR provides expanded
output enable selectability. The logic level of the input state
selector pin, EN_SEL, will determine whether the EN pin
accepts ECL/LVPECL or LVCMOS/LVTTL logic levels.
The output disable mode state pin, OD_MODE, adds
functional flexibility by giving the designer a choice of the
QHG outputs’ polarity when these high−gain outputs are
disabled. For example, with OD_MODE LOW and
EN LOW (LVPECL), the input is passed to the outputs and
the data output equals the data input. If the D input is LOW
when the EN goes HIGH, the next data transition to a HIGH
is ignored and QHG remains LOW and QHG remains
HIGH. The next positive transition of the data input is not
passed on to the QHG outputs under these conditions. The
QHG and QHG outputs remain in their disabled state as long
as the EN input is held HIGH. The EN input has no influence
on the Q or Q outputs and the data inputs are passed on to
these outputs whether EN is HIGH or LOW. When the data
input is HIGH and EN goes HIGH, it will force QHG LOW
and QHG HIGH on the next negative transition of the D
input. This configuration is ideal for crystal oscillator
applications where the oscillator can be free−running and
QHG/QHG gate on and off synchronously without adding
extra counts to the output. See truth table and timing diagram
for detailed ENable functions and options.
The NBLVEP16VR provides a VBB and internal 470
bias resistors from D to VBB and D to VBB for ac coupled
single−ended or differential input signal(s). The VBB_ADJ
pin is used for 2.5 V single−ended operation when it is
connected to VCC. The VBB output current source/sink
capability can support a robust 1.5 mA.
For single−ended input conditions, the unused differential
input is internally connected to VBB as a switching reference
voltage. Decouple VBB and VCC with a 0.01
mF capacitor.
This internal VBB will rebias AC coupled input(s). Inputs D
or D must be signal driven or auto oscillation may result.
Figure 5. Timing Diagram

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