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NBLVEP16VR Fiches technique(PDF) 3 Page - ON Semiconductor

No de pièce NBLVEP16VR
Description  2.5V/3.3V/5V ECL Differential Receiver/Driver with Oscillator Gain Stage and Enabled High Gain Outputs
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NBLVEP16VR Fiches technique(HTML) 3 Page - ON Semiconductor

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NBLVEP16VR
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3
Q
Figure 3. Pinout Diagram (Top View)
D
D
VBB
OD_MODE
EN
CS_SEL
QHG
VEE
QHG
VEEP
EN_SEL
1
2
3
4
56
78
9
10
11
12
13
14
15
16
VCC
NC
VBB_ADJ
NBLVEP16VR
Q
Exposed Pad
(EP)
Q
Figure 4. Die Map
D
D
VBB
OD_MODE
EN
CS_SEL
QHG
VEE
QHG
VEE
EN_SEL
VCC
NC
VBB_ADJ
NBLVEP16VR
Die: 1.16 x 1.19 mm
Q
NC
VBB
VCC
VEEP
(x)
(y)
Bond Pad: 84
mm Diameter
Table 4. PIN DESCRIPTION
Pin No
Name
I/O
Description
1
OD_MODE*
LVCMOS/LVTTL Input (See Table 3)
Selectable Mode of Output Disabled Level
2
D
ECL / LVPECL Input
Clock / Data Input
3
D
ECL / LVPECL Input
Inverted Clock / Data Input
4
VBB
Reference Voltage Output
Reference Voltage Output
5
EN*
ECL / LVPECL or LVCMOS/LVTTL Input
(see Table 3)
Output Enable Synchronous with D and D
6
VBB_ADJ
Adjust Standard VBB Levels Upward When Tied to VCC for
2.5 V Power Supply. Open for 3.3 V and 5 V Power Supply.
7
VEE
Negative Power Supply
Negative Power Supply
8
VEEP
Open or Tied to VEE (See Table 1) Optional 10mA Current
Source For QHG and QHG
9
EN_SEL
LVCMOS / LVTTL Input (See Table 3)
Input LVEL Selector Pin for EN
10
QHG
ECL / LVPECL Output
Inverted High−Gain Output, Gain > 200
11
QHG
ECL / LVPECL Output
High−Gain Output, Gain > 200
12
CS_SEL
Selects Q and Q Current Source Magnitude (see Table 1),
Open or Tied to VEE or VCC
13
VCC
Positive Power Supply
Positive Power Supply
14
NC
No Connect
No Connect
15
Q
ECL / LVPECL Output
ECL/LVPECL Output for Feedback Loop
16
Q
ECL / LVPECL Output
Inverted ECL/LVPECL Output for Feedback Loop
EP
Power Supply (OPT)
Exposed Pad on Package Bottom Should Only Be Con-
nected to VEE or Left Open
*Pins will default LOW when left open.
†Pin will default HIGH when left open.


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