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MC74LVX373 Fiches technique(PDF) 4 Page - ON Semiconductor

No de pièce MC74LVX373
Description  Octal D-Type Latch with 3-State Outputs With 5V−Tolerant Inputs
Download  8 Pages
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74LVX373 Fiches technique(HTML) 4 Page - ON Semiconductor

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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
TA = − 40 to 85°C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Propagation Delay
D to O
VCC = 2.7V
CL = 15pF
CL = 50pF
7.5
10.0
14.5
18.0
1.0
1.0
17.5
21.0
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
5.8
8.3
9.3
12.8
1.0
1.0
11.0
14.5
tPLH,
tPHL
Propagation Delay
LE to O
VCC = 2.7V
CL = 15pF
CL = 50pF
7.7
10.2
15.0
18.5
1.0
1.0
18.5
22.0
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.0
8.5
9.7
13.2
1.0
1.0
11.5
15.0
tPZL,
tPZH
Output Enable Time
OE to O
VCC = 2.7V
CL = 15pF
RL = 1kW
CL = 50pF
7.7
10.2
15.0
18.5
1.0
1.0
18.5
22.0
ns
VCC = 3.3 ± 0.3V
CL = 15pF
RL = 1kW
CL = 50pF
6.0
8.5
9.7
13.2
1.0
1.0
11.5
15.0
tPLZ,
tPHZ
Output Disable Time
OE to O
VCC = 2.7V
CL = 50pF
RL = 1kW
9.8
18.0
1.0
21.0
ns
VCC = 3.3 ± 0.3V
CL = 50pF
RL = 1kW
8.2
12.8
1.0
14.5
tOSHL
tOSLH
Output−to−Output Skew
(Note 1)
VCC = 2.7V
CL = 50pF
VCC = 3.3 ±0.3V
CL = 50pF
1.5
1.5
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
TA = − 40 to 85°C
Symbol
Parameter
Min
Typ
Max
Min
Max
Unit
Cin
Input Capacitance
4
10
10
pF
Cout
Maximum Three−State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
27
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per latch). CPD is used to determine the
no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.5
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
TA = − 40 to 85°C
Symbol
Parameter
Test Conditions
Typ
Limit
Limit
Unit
tw(h)
Minimum Pulse Width, LE
VCC = 2.7V
VCC = 3.3 ±0.3V
6.5
5.0
7.5
5.0
ns
tsu
Minimum Setup Time, D to LE
VCC = 2.7V
VCC = 3.3 ±0.3V
6.0
4.0
6.0
4.0
ns
th
Minimum Hold Time, D to LE
VCC = 2.7V
VCC = 3.3 ±0.3V
1.0
1.0
1.0
1.0
ns


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