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TLV767-Q1 Fiches technique(PDF) 18 Page - Texas Instruments |
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TLV767-Q1 Fiches technique(HTML) 18 Page - Texas Instruments |
18 / 28 page Device IN OUT GND COUT CIN Schottky Diode Internal Body Diode 18 TLV767-Q1 SBVS381 – APRIL 2020 www.ti.com Product Folder Links: TLV767-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Application Information (continued) 8.1.4 Reverse Current Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. • If the device has a large COUT and the input supply collapses with little or no load current • The output is biased when the input supply is not established • The output is biased above the input supply If reverse current flow is expected in the application, external protection is recommended to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. Figure 38 shows one approach for protecting the device. Figure 38. Example Circuit for Reverse Current Protection Using a Schottky Diode 8.1.5 Feed-Forward Capacitor (CFF) For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report. CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at frequency fP. CFF zero and pole frequencies can be calculated from the following equations: fZ = 1 / (2 × π × CFF × R1) (4) fP = 1 / (2 × π × CFF × (R1 || R2)) (5) CFF ≥ 10 pF is required for stability if the feedback divider current is less than 5 µA. Equation 6 calculates the feedback divider current. IFB_Divider = VOUT / (R1 + R2) (6) To avoid startup time increases from CFF, limit the product CFF × R1 < 50 µs. For an output voltage of 0.8 V with the FB pin tied to the OUT pin, no CFF is used. |
Numéro de pièce similaire - TLV767-Q1 |
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Description similaire - TLV767-Q1 |
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