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MSP430FG4619 Fiches technique(PDF) 35 Page - Texas Instruments

No de pièce MSP430FG4619
Description  MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers
Download  116 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430FG4619 Fiches technique(HTML) 35 Page - Texas Instruments

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C
VREF+
1 mF
0
1ms
10ms
100ms
t
REFON
t
REFON » .66xC
[ms]withC
in
VREF+
VREF+
mF
100 mF
10 mF
35
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508K – APRIL 2006 – REVISED MAY 2020
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Specifications
Copyright © 2006–2020, Texas Instruments Incorporated
(1)
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10-µF tantalum and 100-nF ceramic.
(2)
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
5.29
12-Bit ADC, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF+
Positive built in reference voltage
output
REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
VCC = 3 V
2.4
2.5
2.6
V
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
VCC = 2.2 V, 3 V
1.44
1.5
1.56
AVCC(min)
AVCC minimum voltage, Positive
built in reference active
REF2_5V = 0, IVREF+max ≤ IVREF+ ≤ IVREF+min
2.2
V
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ –0.5 mA
2.8
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ – 1 mA
2.9
IVREF+
Load current out of VREF+
terminal
VCC = 2.2 V
0.01
–0.5
mA
VCC = 3 V
0.01
–1
IL(VREF+)
Load-current regulation, VREF+
terminal
IVREF+ = 500 µA ±100 µA,
Analog input voltage
≈ 0.75 V,
REF2_5V = 0
VCC = 2.2 V
±2
LSB
VCC = 3 V
±2
IVREF+ = 500 µA ±100 µA,
Analog input voltage
≈ 1.25 V,
REF2_5V = 1
VCC = 3 V
±2
IDL(VREF+)
Load current regulation, VREF+
terminal
IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, Ax ≈ 0.5 × VREF+,
Error of conversion result
≤ 1 LSB
VCC = 3 V
20
ns
CVREF+
Capacitance at pin VREF+
(1)
REFON = 1,
0 mA
≤ IVREF+ ≤ IVREF+max
VCC = 2.2 V, 3 V
5
10
µF
TREF+
Temperature coefficient of built-
in reference
IVREF+ is a constant in the range of
0 mA
≤ IVREF+ ≤ 1 mA
VCC = 2.2 V, 3 V
±100 ppm/°C
tREFON
Settling time of internal reference
voltage (see Figure 5-23 ) (2)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
17
ms
Figure 5-23. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+


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