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MSP430F5310 Fiches technique(PDF) 42 Page - Texas Instruments

No de pièce MSP430F5310
Description  MSP430F5310, MSP430F530x Mixed-Signal Microcontrollers
Download  109 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430F5310 Fiches technique(HTML) 42 Page - Texas Instruments

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Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R15
General-Purpose Register
R14
42
MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304
SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020
www.ti.com
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Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304
Detailed Description
Copyright © 2010–2020, Texas Instruments Incorporated
6
Detailed Description
6.1
CPU (Link to User's Guide)
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Figure 6-1. Integrated CPU Registers


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