CDC9843

PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER

WITH 3-STATE OUTPUTS

SCAS559C – DECEMBER 1995 – REVISED OCTOBER 1996

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

CLOCK DRIVER CIRCUITS

Duty Cycle

VOLTAGE WAVEFORMS

tr

tf

tc

2.4 V

1.5 V

0.4 V

LOAD CIRCUIT

From Output

Under Test

CL = 20 pF

(see Note A)

500

Ω

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

v 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,

tf ≤ 2.5 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

HCLK-to-HCLK Skew

Skew

1.5 V

1.5 V

VOH

GND

VOH

GND

CPU Clock

(HCLK)

CPU Clock

(HCLK)

PCLK-to-PCLK Skew

Skew

1.5 V

1.5 V

VOH

GND

VOH

GND

PCI Clock

(PCLK)

PCI Clock

(PCLK)

Offset

1.5 V

1.5 V

VOH

GND

CPU Clock

(HCLK)

PCI Clock

(PCLK)

VOH

GND

Offset

HCLK-to-PCLK Offset