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A8483 Fiches technique(PDF) 5 Page - Allegro MicroSystems

No de pièce A8483
Description  1.2 MHz Step-up Converter for Display Bias Supply
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Fabricant  ALLEGRO [Allegro MicroSystems]
Site Internet  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A8483 Fiches technique(HTML) 5 Page - Allegro MicroSystems

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A8483-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
Allegro MicroSystems, Inc.
1.2 MHz Step-up Converter for Display Bias Supply
A8483
5
Dimming Control
Display dimming can be achieved by controlling the output
voltage, VOUT, using the FB pin. The circuitry behind the FB
pin is flexible, to accommodate a variety of schemes used for
dimming:
• Adjust the duty cycle of the pulse train applied to the FB pin
through resistor R3, as shown in figure 11. Capacitor Cf is
used to generate the average voltage level. Variation of output
voltage with PWM duty cycle is shown in figure 9.
• Apply a constant dc voltage to the FB pin through resistor
R3, as shown in figure 12. Variation of output voltage with dc
voltage are shown in figure 10.
• Selection of the resistor connected between the FB pin and
GND, as shown in figure 12 for OLED applications, and in
figure 13 for WLED applications. The voltage drop across
the transistor should be negligible compared to the FB sense
voltage.
Soft Start
Output voltage rise time at power-on can be extended by using a
soft start circuit, such as the one shown in figure 14 for an OLED
application, and in figure 16 for a WLED application. At power-
on, the device duty cycle begins initially at a high level, drawing
a large current from the input supply, VIN. The soft-start circuits
shown can reduce the level of current flow by controlling the FB
pin.
When a signal is applied to the EN pin, capacitor C3 discharges,
pulling the FB pin high, and reducing VOUT to a minimum.
When the EN signal is removed, C3 recharges and as it does, the
voltage drop across R3 reduces, allowing the device duty cycle to
Figure 9. PWM Dimming Control of Duty Cycle. Performance of 5 V input
circuit shown in figure 3.
3
5
7
9
11
13
15
17
10
20
30
40
50
60
70
80
90
Duty Cycle (%)
0
2
4
6
8
10
12
14
16
18
20
0.20.4
0.60.8
1
VC (V)
Figure 10. DC Voltage Dimming Control of Duty Cycle. Performance of
circuit shown in figure 11.
Figure 12. OLED Dimming Control. Single-bit resolution using
external transistor.
A8483
VIN
SW
EN
VC
GND
FB
C1
1 µF
1
23
5
4
L1
10 µH
Q1
D1
VOUT
C2
10 µF
R2
47 k
Ω
R1
560 k
Ω
Enable
R3
47 k
Ω
Cf
1 nF
VSUPPLY
Li-ion
2.5 V to
5.5 V
Figure 13. WLED Dimming Control. Single-bit resolution using
external transistor.
A8483
VIN
SW
EN
VC
GND
FB
C1
1 µF
1
23
5
4
L1
10 µH
Q1
D1
VOUT
C2
0.22 µF
Enable
R2
80
Ω
R1
80
Ω
VSUPPLY
Li-ion
2.5 V to
5.5 V
Applications Information
A8483
VIN
SW
EN
VC
GND
FB
C1
1 µF
1
23
5
4
L1
10 µH
D1
VOUT
C2
1 µF
R2
47 k
Ω
R1
560 k
Ω
Enable
R3
160 k
Ω
Cf
Cf for PWM dimming only
1 nF
Analog Voltage or
PWM 10 kHz
VSUPPLY
Li-ion
2.5 V to
5.5 V
Figure 11. OLED Bias Supply. Use for low-noise PWM dimming,
or with analog voltage through the FB pin.


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