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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ISL8102 Fiches technique(PDF) 23 Page - Intersil Corporation |
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ISL8102 Fiches technique(HTML) 23 Page - Intersil Corporation |
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23 / 27 page  23 FN9247.0 October 19, 2005 amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 23 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the per-channel switching frequency, FSW. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ∆I, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ∆VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output- voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount The filter capacitor must have sufficiently low ESL and ESR so that ∆V < ∆VMAX. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see Interleaving and Equation 2), a voltage develops across the bulk capacitor ESR equal to IC,PP(ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance. Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ∆VMAX. This places an upper limit on inductance. Equation 31 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 32 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. 0 FP1 FZ2 OPEN LOOP E/A GAIN FZ1 FP2 FLC FCE COMPENSATION GAIN FREQUENCY MODULATOR GAIN FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN CLOSED LOOP GAIN 20 dMAX V ⋅ IN VOSC --------------------------------- log 20 R2 R1 -------- log LOG F0 GMOD GFB GCL ∆V ESL () di dt ----- ⋅ ESR () ∆I ⋅ + ≈ (EQ. 29) L ESR () VIN NV ⋅ OUT – V OUT ⋅ FSW VIN VPP MAX () ⋅⋅ -------------------------------------------------------------------- ≥ (EQ. 30) L 2NCVO ⋅⋅⋅ ∆I ()2 --------------------------------- ∆V MAX ∆IESR ⋅ () – ⋅ ≤ (EQ. 31) L 1.25 () NC ⋅⋅ ∆I ()2 ---------------------------------- ∆V MAX ∆I ESR ⋅ () – VIN VO – ⋅⋅ ≤ (EQ. 32) ISL8102 |
Numéro de pièce similaire - ISL8102 |
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Description similaire - ISL8102 |
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