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ISL6566A Fiches technique(PDF) 19 Page - Intersil Corporation |
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ISL6566A Fiches technique(HTML) 19 Page - Intersil Corporation |
19 / 28 page 19 FN9200.2 July 27, 2005 General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. Power Stages The first step in designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which each phase handles between 25 and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat- dissipating surfaces. MOSFETS The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency, the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for power loss in the lower MOSFET is simple, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 15, IM is the maximum continuous output current, IPP is the peak-to-peak inductor current (see Equation 1), and d is the duty cycle (VOUT/VIN). An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON), the switching frequency, fS, and the length of dead times, td1 and td2, at the beginning and the end of the lower-MOSFET conduction interval respectively. The total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upper- MOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverse- recovery charge, Qrr, and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 17, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 18, the approximate power loss is PUP,2. A third component involves the lower MOSFET reverse- recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lower- MOSFET body diode can recover all of Qrr, it is conducted 0A 0V 2ms/DIV OUTPUT CURRENT, 50A/DIV FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE FSW = 500kHz OUTPUT VOLTAGE, 500mV/DIV PLOW 1 , rDS ON () IM N ------ 2 1d – () ILPP , 2 1d – () 12 -------------------------------- + = (EQ. 15) PLOW 2 , VDON () fS IM N ------ IPP 2 --------- + t d1 IM N ------ IPP 2 --------- – td2 + = (EQ. 16) PUP 1, VIN IM N ------ IPP 2 --------- + t1 2 ---- fS ≈ (EQ. 17) PUP 2 , VIN IM N ------ IPP 2 --------- – t2 2 ---- fS ≈ (EQ. 18) PUP 2 , VIN IM N ------ IPP 2 --------- – t2 2 ---- fS ≈ ISL6566A |
Numéro de pièce similaire - ISL6566A |
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Description similaire - ISL6566A |
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