Moteur de recherche de fiches techniques de composants électroniques
  French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

ISL6566 Fiches technique(PDF) 15 Page - Intersil Corporation

No de pièce ISL6566
Description  Three-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6566 Fiches technique(HTML) 15 Page - Intersil Corporation

Back Button ISL6566 Datasheet HTML 11Page - Intersil Corporation ISL6566 Datasheet HTML 12Page - Intersil Corporation ISL6566 Datasheet HTML 13Page - Intersil Corporation ISL6566 Datasheet HTML 14Page - Intersil Corporation ISL6566 Datasheet HTML 15Page - Intersil Corporation ISL6566 Datasheet HTML 16Page - Intersil Corporation ISL6566 Datasheet HTML 17Page - Intersil Corporation ISL6566 Datasheet HTML 18Page - Intersil Corporation ISL6566 Datasheet HTML 19Page - Intersil Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 28 page
background image
15
FN9178.3
July 25, 2005
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Positive Offset (connect ROFS to GND):
For Negative Offset (connect ROFS to VCC):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption.
The DAC mode the ISL6566 is operating in determines how
the controller responds to a dynamic VID change. When in
VRM10 mode the ISL6566 checks the VID inputs six times
every switching cycle. If a new code is established and it
stays the same for 3 consecutive readings, the ISL6566
recognizes the change and increments the reference.
Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or
decrementing one VID step at a time. In VRM10 setting, the
ISL6566 will immediately change the reference to the new
requested value as soon as the request is validated; in
cases where the reference step is too large, the sudden
change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VRM10 VID change, a VID step change smoothing
network is required for an ISL6566 based voltage regulator.
This network is composed of a 1k
Ω internal resistor between
the output of DAC and the capacitor CREF, between the REF
pin and ground. The selection of CREF is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every TVID, the relationship between CREF and TVID is
given by Equation 10.
As an example, for a VID step change rate of 5
µs per bit, the
value of CREF is 22nF based on Equation 10.
When running in VRM9 or AMD Hammer operation, the
ISL6566 responds slightly different to a dynamic VID change
than when in VRM10 mode. In these modes the VID code can
be changed by more than a 1-bit step at a time. Once the
controller receives the new VID code it waits half of a phase
cycle and then begins slewing the DAC 12.5mV every phase
cycle, until the VID and DAC are equal. Thus, the total time
required for a VID change, tDVID, is dependent on the switching
frequency (fS), the size of the change (∆VVID), and the time
required to register the VID change. The one-cycle addition in
the tDVID equation is due to the possibility that the VID code
change may occur up to one full switching cycle before being
recognized. The approximate time required for a ISL6566-
based converter in AMD Hammer configuration running at fS =
335kHz to make a 1.1V to 1.5V reference voltage change is
about 100
µs, as calculated using the following equation.
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
GND
ROFS
RFB
VDIFF
ISL6566
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
VOFS
+
-
IOFS
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
VCC
ROFS
RFB
VDIFF
ISL6566
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
VOFS
+
-
IOFS
(EQ. 8)
ROFS
0.5 RFB
×
VOFFSET
--------------------------
=
(EQ. 9)
ROFS
1.5 RFB
×
VOFFSET
--------------------------
=
CREF
0.004X TVID
=
(EQ. 10)
(EQ. 11)
tDVID
1
fS
-----
VVID
0.0125
------------------ 1.5
+


=
ISL6566


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn