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TP3054WM-X Fiches technique(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce TP3054WM-X
Description  Extended Temperature Serial Interface CODEC/Filter COMBO Family
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP3054WM-X Fiches technique(HTML) 3 Page - National Semiconductor (TI)

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Pin Descriptions (Continued)
Symbol
Function
MCLK
X
Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
R. Best
performance is realized from
synchronous operation.
FS
X
Transmit frame sync pulse input which
enables BCLK
X to shift out the PCM
data on D
X.FSX is an 8 kHz pulse
train, see Figure 2 and Figure 3 for
timing details.
BCLK
X
The bit clock which shifts out the PCM
data on D
X. May vary from 64 kHz to
2.048 MHz, but must be synchronous
with MCLK
X.
D
X
The TRI-STATE® PCM data output
which is enabled by FS
X.
TS
X
Open drain output which pulses low
during the encoder time slot.
GS
X
Analog output of the transmit input
amplifier. Used to externally set gain.
VF
XI
Inverting input of the transmit input
amplifier.
VF
XI
+
Non-inverting input of the transmit input
amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initial-
izes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
X and VFRO
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK
R/PDN
pin and FS
X
and/or FS
R
pulses must be
present. Thus, 2 power-down control modes are available.
The first is to pull the MCLK
R/PDN pin high; the alternative is
to hold both FS
X and FSR inputs continuously low — the
device will power-down approximately 1 ms after the last
FS
X or FSR pulse. Power-up will occur on the first FSX or
FS
R pulse. The TRI-STATE PCM data output, DX, will remain
in the high impedance state until the second FS
X pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLK
X
and the MCLK
R/PDN pin can be used as a power-down
control. A low level on MCLK
R/PDN powers up the device
and a high level powers down the device. In either case,
MCLK
X will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be applied
to BCLK
X and the BCLKR/CLKSEL can be used to select the
proper internal divider for a master clock of 1.536 MHz,
1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the
device automatically compensates for the 193rd clock pulse
each frame.
With a fixed level on the BCLK
R/CLKSEL pin, BCLKX will be
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
R/
CLKSEL. In this synchronous mode, the bit clock, BCLK
X,
may be from 64 kHz to 2.048 MHz, but must be synchronous
with MCLK
X.
Each FS
X pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X output on the positive edge of BCLKX. After 8 bit
clock periods, the TRI-STATE D
X output is returned to a high
impedance state. With an FS
R pulse, PCM data is latched
via the D
R input on the negative edge of BCLKX (or BCLKR
if running). FS
X
and FS
R
must be synchronous with
MCLK
X/R.
TABLE 1. Selection of Master Clock Frequencies
BCLK
R/CLKSEL
Master Clock
Frequency Selected
TP3057
TP3054
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
0
1.536 MHz or
2.048 MHz
1.544 MHz
1
2.048 MHz
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK
X
and MCLK
R
must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK
R should be synchronous
with MCLK
X, which is easily achieved by applying only static
logic levels to the MCLK
R/PDN pin. This will automatically
connect MCLK
X to all internal MCLKR functions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS
X starts each encoding cycle and must be synchronous
with MCLK
X and BCLKX.FSR starts each decoding cycle
and must be synchronous with BCLK
R. BCLKR must be a
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK
X and BCLKR may operate from
64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS
X and FSR, must be one bit clock period long, with
timing relationships specified in Figure 2. With FS
X high
during a falling edge of BCLK
X, the next rising edge of
BCLK
X enables the DX TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the D
X output. With FSR high during a falling edge
of BCLK
R (BCLKX in synchronous mode), the next falling
edge of BCLK
R latches in the sign bit. The following seven
falling edges latch in the seven remaining bits. All four de-
vices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.
www.national.com
3


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