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CS5504 Fiches technique(PDF) 10 Page - Cirrus Logic |
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CS5504 Fiches technique(HTML) 10 Page - Cirrus Logic |
10 / 24 page GENERAL DESCRIPTION The CS5504 is a low power, 20-bit, monolithic CMOS A/D converter designed specifically for measurement of dc signals. The CS5504 in- cludes a delta-sigma charge-balance converter, a voltage reference, a calibration micro controller with SRAM, a digital filter and a serial interface. The CS5504 is optimized to operate from a 32.768 kHz crystal but can be driven by an ex- ternal clock whose frequency is between 30 kHz and 330 kHz. When the digital filter is operated with a 32.768 kHz clock, the filter has zeros pre- cisely at 50 and 60 Hz line frequencies and multiples thereof. The CS5504 uses a "start convert" command to latch the input channel selection and to start a convolution cycle on the digital filter. Once the filter cycle is completed, the output port is up- dated. When operated with a 32.768 kHz clock the ADC converts and updates its output port at 20 samples/sec. The output port operates in a synchronous externally-clocked interface format. THEORY OF OPERATION Basic Converter Operation The CS5504 A/D converter has three operating states. These are stand-by, calibration, and con- version. When power is first applied, an internal power-on reset delay of about 10 ms resets all of the logic in the device. The oscillator must then begin oscillating before the device can be con- sidered functional. After the power-on reset is applied, the device enters the wake-up period for 1800 clock cycles after clock is present. This allows the delta-sigma modulator and other cir- cuitry (which are operating with very low currents) to reach a stable bias condition prior to entering into either the calibration or conversion states. During the 1800 cycle wake-up period, the device can accept an input command. Execu- tion of this command will not occur until the complete wake-up period elapses. If no com- mand is given, the device enters the standby state. Calibration After the initial application of power, the CS5504 must enter the calibration state prior to performing accurate conversions. During calibra- tion, the chip executes a two-step process. The device first performs an offset calibration and then follows this with a gain calibration. The two calibration steps determine the zero refer- ence point and the full scale reference point of the converter’s transfer function. From these points it calibrates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions. The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at power- on are recognized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. If CAL and CONV become active (high) during the 1800 clock cycle wake-up time, the con- verter will wait until the wake-up period elapses before executing the calibration. If the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately if CAL and CONV become active. The calibration lasts for 3246 clock cycles. Calibration coefficients are then retained in the SRAM (static RAM) for use during conversion. The states of A0 and BP/UP are ignored during calibration but should remain stable throughout the calibration period to minimize noise. When conversions are performed in unipolar mode or in bipolar mode, the converter uses the same calibration factors to compute the digital CS5504 10 DS126F1 CS5504 10 DS126F2 |
Numéro de pièce similaire - CS5504 |
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Description similaire - CS5504 |
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