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MC10SX1125 Fiches technique(PDF) 2 Page - ON Semiconductor |
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MC10SX1125 Fiches technique(HTML) 2 Page - ON Semiconductor |
2 / 5 page MC10SX1125 MOTOROLA ECLinPS and ECLinPS Lite DL140 — Rev 3 2 FUNCTION TABLE Pin Function CAZN Auto-zero capacitor pin. A capacitor between this pin and CAZP cancels any offset inherent to the limiting amplifier. CAZP Auto-zero capacitor pin. A capacitor between this pin and CAZN cancels any offset inherent to the limiting amplifier. GNDA Analog ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the same potential. Din, Din Differential data input. VCCA Analog power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the same potential. CLD Filter capacitor for the level detect comparator. Capacitor should be connected to VCCA. Disable When asserted LOW, or left open and pulled LOW via the input pulldown resistor, the output buffer will be enabled and will respond to the input stimulus on the Din input. Forcing Disable HIGH will force the Dout output LOW and its complimentary output HIGH. LOS Loss of signal. This output will go HIGH when the input signal falls below (Vset/100) mVP-P. GNDE Digital ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the same potential. Dout, Dout Differential data outputs. VCCE Digital power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the same potential. Vref Reference voltage for threshold level set voltage division network (2.64V). Vset Input threshold level detect setting input. Input generated from voltage divider between Vref and GNDA. Figure 1. Typical Operating Circuit 16 1 CAZN Vset 15 2 CAZP Vref 14 3 GNDA VCCE 13 4 Din Dout 12 5 Din Dout 11 6 VCCA GNDE 10 7 CLD LOS 9 8 Disable LOS R1 R2 50 DATA OUT 50 5V 3V 50 LEVEL DETECT OUT 50 Cbypass CAZ Cin Cin DATA IN 5V CAZ Cbypass |
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Description similaire - MC10SX1125 |
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