MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–311

REV 5

3/93

9-Bit Latch ECL/TTL

Translator

The MC10H/100H603 is a 9–bit, dual supply ECL to TTL translator.

Devices in the Motorola 9–bit translator series utilize the 28–lead PLCC for

optimal power pinning, signal flow–through and electrical performance.

The devices feature a 48 mA TTL output stage, and AC performance is

specified into both a 50 pF and 200 pF load capacitance. Latching is

controlled by Latch Enable (LEN), and Master Reset (MR) resets the

latches. A HIGH on OEECL sends the outputs into the high impedance

state. All control inputs are ECL level.

The 10H version is compatible with MECL 10H ECL logic levels. The

100H version is compatible with 100K levels.

• 9–Bit Ideal for Byte–Parity Applications

• 3–State TTL Outputs

• Flow–Through Configuration

• Extra TTL and ECL Power Pins to Minimize Switching Noise

• Dual Supply

• 6.0 ns Max Delay into 50 pF, 12 ns into 200 pF (all outputs switching)

• PNP TTL Inputs for Low Loading

LOGIC SYMBOL

DQ

EN

DQ

EN

DQ

EN

DQ

EN

DQ

EN

DQ

EN

DQ

EN

DQ

EN

DQ

EN

OEECL

D0

D1

D2

D3

D4

D5

D6

D7

D8

LEN

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

TTL

ECL

MC10H603

MC100H603

Pinout: 28–Lead PLCC (Top View)

PIN NAMES

PIN

FUNCTION

GND

VCCE

VCCT

VEE

D0 – D8

Q0 – Q8

OEECL

LEN

MR

TTL Ground (0 V)

ECL VCC (0 V)

TTL Supply (+ 5.0 V)

ECL Supply (– 5.2 / – 4.5 V)

Data Inputs (ECL)

Data Outputs (TTL)

3-State Control (ECL)

Latch Enable (ECL)

Master Reset (ECL)

Q4

56

78

9

10

11

25

24

23

22

21

20

19

Q3

VCCT

Q2

GND

Q1

Q0

VCCE

D8

D7

D6

D5

D4

D3

26

27

28

2

3

4

18

17

16

14

13

12

15

Q5 GND VCCT Q6 GND Q7 Q8

MR LEN OEECL VEE D0 D1

D2

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

D

L

H

X

X

X

TRUTH TABLE

LEN

L

L

H

X

X

MR

L

L

L

H

X

Q

L

H

Q0

L

Z

OEECL

L

L

L

L

H