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KM732V696L Fiches technique(PDF) 8 Page - Samsung semiconductor |
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KM732V696L Fiches technique(HTML) 8 Page - Samsung semiconductor |
8 / 16 page PRELIMINARY KM732V696/L 64Kx32 Synchronous SRAM Rev 1.0 - 8 - May 1997 TEST CONDITIONS Parameter Value Input Pulse Level (for 3.3V I/O) 0 to 3V Input Pulse Level (for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) 2ns Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) 2ns Input and Output Timing Reference Levels(for 3.3V I/O) 1.5V Input and Output Timing Reference Levels(for 2.5V I/O) VDDQ/2 Output Load See Fig. 1 (TA=0 to 70 °C, VDD=3.3V-5%/+10%, VDDQ=3.3V-5%/+10%, or VDD=3.3V±5%, VDDQ=2.5V+0.4V/-0.13V) Output Load(A) Output Load(B), (3.3V I/O) (for tLZC, tLZOE, tHZOE & tHZC) Dout Z0=50 Ω Dout 353 Ω 5pF* +3.3V 319 Ω * Capacitive Load consists of all components of Fig. 1 30pF* * Including Scope and Jig Capacitance the test environment. Output Load(C), (2.5V I/O) (for tLZC, tLZOE, tHZOE & tHZC) Dout 1538 Ω 5pF* +2.5V 1667 Ω * Including Scope and Jig Capacitance RL=50 Ω VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O |
Numéro de pièce similaire - KM732V696L |
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Description similaire - KM732V696L |
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