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ST7920
C2.0c
3/47
2001/10/18
系統方塊圖
系統方塊圖
系統方塊圖
系統方塊圖
Timing
Generator
33/49-
bit shift
register
Common
Signal
Driver
Display
Data RAM
(DDRAM)
60 x 16 bits
64-bit
latch
circuit
Segment
Signal
Driver
64-bit
shift
register
LCD Drive
Voltage
Selector
CLK
Instruction
Register (IR)
Instruction
Decoder
Reset
Circuit
MPU
Interface
Input/
Output
Buffer
Address
Counter
Character
Generator
ROM
(CGROM)
2M bits
Character
Generator
RAM
(CGRAM)
1024 bits
Cursor
Blink
Scroll
Controller
Data
Register
(DR)
Busy
Flag
Parallel/Serial converter
and
Attribute Circuit
VDD
V0
V1
V2
V3
V4
RESI
RESO
CL1
CL2
M
DOUT
COM1 to
COM33
SEG1 to
SEG64
RS
RW
E
DB4 to
DB7
DB0 to
DB3
Half size
Character
ROM
(HCGROM)
1024x16 bits
XRESET
Graphic
RAM
(GRAM)
1024 x 16
bits
XOFF
Vss
PSB