5

6

7

8

9

10

11

Q3

Q3

VCCO

R2

CE2

D2

R3

LOGIC DIAGRAM

CE3

D3

S12

VEE

CC

S03

D0

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

Q2

Q2

VCC

Q1

Q1

Q0

Q0

CE0

R0

D1

CE1

R1

NC

VCCO

D3

CE3

R3

D2

CE2

R2

S03

S12

CC

R1

CE1

D1

R0

CE0

D0

Q3

Q3

Q2

Q2

Q1

Q1

Q0

Q0

S

D

Q

Q

R

S

D

Q

Q

R

R

D

Q

Q

S

R

D

Q

Q

S

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 3

7/96

4Bit D FlipFlop

The MC10E/100E131 is a quad master-slave D-type flip-flop with

differential outputs. Each flip-flop may be clocked separately by holding

Common Clock (CC) LOW and using the Clock Enable (CE) inputs for

clocking. Common clocking is achieved by holding the CE inputs LOW

and using CC to clock all four flip-flops. In this case, the CE inputs perform

the function of controlling the common clock, to each flip-flop.

Individual asynchronous resets are provided (R). Asynchronous set

controls (S) are ganged together in pairs, with the pairing chosen to

reflect physical chip symmetry.

Data enters the master when both CC and CE are LOW, and transfers

to the slave when either CC or CE (or both) go HIGH.

PIN NAMES

Pin

Function

D0 – D3

Data Inputs

CE0 – CE3

Clock Enables (Individual)

R0 – R3

Resets

CC

Common Clock

S03, S12

Sets (paired)

Q0 – Q3

True Outputs

Q0 – Q3

Inverting Outputs

MC10E131

MC100E131

4-BIT

D FLIP-FLOP

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02