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74AUP1G79GW Fiches technique(PDF) 4 Page - NXP Semiconductors |
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74AUP1G79GW Fiches technique(HTML) 4 Page - NXP Semiconductors |
4 / 20 page 9397 750 14682 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 12 September 2005 4 of 20 Philips Semiconductors 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger 7.2 Pin description 8. Functional description 8.1 Function table [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. 9. Limiting values Table 4: Pin description Symbol Pin Description TSSOP5 XSON6 D 1 1 data input D CP 2 2 clock pulse input CP GND 3 3 ground (0 V) Q 4 4 data output Q n.c. - 5 not connected VCC 5 6 supply voltage Table 5: Function table [1] Input Output CP D Q ↑ LL ↑ HH LX q Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V IIK input clamping current VI <0V - −50 mA VI input voltage [1] −0.5 +4.6 V IOK output clamping current VO >VCC or VO <0V - ±50 mA VO output voltage active mode [1] −0.5 VCC + 0.5 V Power-down mode [1] −0.5 +4.6 V IO output current VO =0 VtoVCC - ±20 mA ICC quiescent supply current - +50 mA |
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