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CS61318-IP Fiches technique(PDF) 6 Page - Cirrus Logic |
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CS61318-IP Fiches technique(HTML) 6 Page - Cirrus Logic |
6 / 28 page CS61318 6 DS441PP2 E1 SWITCHING CHARACTERISTICS (TA = -40 °C to 85°C; TV+, RV+ = 5.0 V ±5%; GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3) Notes: 16. MCLK provided by an external source to TCLK. 17. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached. 18. At max load of 1.6mA and 50pF. 19. Host Mode (CLKE = 1). 20. Host Mode (CLKE = 0). Parameter Symbol Min Typ Max Units TCLK Frequency ftclk -2.048 - MHz TCLK Duty Cycle (Note12) tpwh2/tpw2 40 50 60 % MCLK Frequency (Note 16) fmclk -2.048 - MHz RCLK Duty Cycle (Note 17) tpwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 18) tr -- 85 ns Fall Time, All Digital Outputs (Note 19) tf -- 85 ns TPOS/TNEG to TCLK Falling Setup Time tsu2 25 - - ns TCLK Falling to TPOS/TNEG Hold Time th2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 19) tsu1 100 194 - ns RPOS/RNEG Valid Before RCLK Rising (Note 20) tsu1 100 194 - ns RPOS/RNEG Valid After RCLK Falling (Note 19) th1 100 194 - ns RPOS/RNEG Valid After RCLK Rising (Note 20) th1 100 194 - ns Any Digital Output t r t f 10% 10% 90% 90% Figure 1. Signal Rise and Fall Characteristics RCLK tpw1 tpwl1 tpwh1 (CLKE = 1) (CLKE = 0) RCLK RPOS RNEG su1 h1 tt Figure 2. Recovered Clock and Data Switching Characteristics TCLK TPOS/TNEG t su2 t h2 t pwh2 t pw2 Figure 3. Transmit Clock and Data Switching Characteristics |
Numéro de pièce similaire - CS61318-IP |
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Description similaire - CS61318-IP |
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