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ADRF5721 Fiches technique(PDF) 11 Page - Analog Devices

No de pièce ADRF5721
Description  Silicon Digital Attenuator
Download  17 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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Data Sheet
ADRF5721
Rev. 0 | Page 11 of 17
THEORY OF OPERATION
The ADRF5721 incorporates a 4-bit fixed attenuator array that
offers an attenuation range of 30 dB in 2 dB steps. An integrated
driver provides both serial and parallel mode control of the
attenuator array (see Figure 22).
Note that when referring to a single function of a multifunction
pin in this section, only the portion of the pin name that is
relevant is mentioned. For full pin names of the multifunction
pins, refer to the Pin Configuration and Function Descriptions
section.
POWER SUPPLY
The ADRF5721 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
The power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up VSS.
4. Apply the digital control inputs. The relative order of the
digital control inputs is not important. However, powering
the digital control inputs before the VDD supply can
inadvertently forward bias and damage the internal ESD
protection structures.
5. Apply an RF input signal to ATTIN or ATTOUT.
The power-down sequence is the reverse order of the power up
sequence.
RF INPUT AND OUTPUT
Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V.
DC blocking is not required at the RF ports when the RF line
potential is equal to 0 V.
The RF ports are internally matched to 50 Ω. Therefore,
external matching components are not required.
The ADRF5721 supports bidirectional operation at a lower
power level. The power handling of the ATTIN and ATTOUT
ports are different. Therefore, the bidirectional power handling is
defined by the ATTOUT port. Refer to the RF input power
specifications in Table 1.
SERIAL OR PARALLEL MODE SELECTION
The ADRF5721 can be controlled in either serial or parallel mode
by setting the PS pin to high or low, respectively (see Table 6).
Table 6. Mode Selection
PS
Control Mode
Low
Parallel
High
Serial
Table 7. Truth Table
Digital Control Input1
Attenuation State (dB)
D5
D4
D3
D2
D1
D0
Low
Low
Low
Low
Don’t care
Don’t care
0 (reference)
Low
Low
Low
High
Don’t care
Don’t care
2
Low
Low
High
Low
Don’t care
Don’t care
4
Low
High
Low
Low
Don’t care
Don’t care
8
High
Low
Low
Low
Don’t care
Don’t care
16
High
High
High
High
Don’t care
Don’t care
30
1
Any combination of the control voltage input states shown in Table 7 provides an attenuation equal to the sum of the bits selected.
Figure 22. Simplified Circuit Diagram
D
Q
D
Q
D
Q
D
Q
D
Q
PARALLEL OR SERIAL SELECT
6-BIT OR 8-BIT LATCH
D
Q
D
SERIN
CLK
PS
LE
D2
D3
D4
D5
Q
D
Q
RF
INPUT
RF
OUTPUT
SEROUT
2dB
4dB
8dB
16dB


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