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ADP1071-1 Datasheet(Fiches technique) 24 Page - Analog Devices

Numéro de pièce ADP1071-1
Description  Isolated Synchronous Flyback Controller
Télécharger  27 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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ADP1071-1 Datasheet(HTML) 24 Page - Analog Devices

 
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ADP1071-1/ADP1071-2
Data Sheet
Rev. B | Page 24 of 27
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
0V
RATED PEAK VOLTAGE
Figure 26. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
Figure 27. Unipolar AC Waveform
0V
RATED PEAK VOLTAGE
Figure 28. DC Waveform
LAYOUT GUIDELINES
The layout guidelines for the primary side are as follows:
1.
Ground all the capacitors to their respective grounds. For
example, ground the VREG1 capacitor to AGND1.
2.
Use the CS pin and the AGND1 pin to differentially sense
the primary current measurement through the sense
resistor. Do not cross the CS and AGND1 traces for current
sensing across any switch nodes.
3.
Place a capacitor (33 pF to 470 pF typical) close to the
CS pin, connected to AGND1.
4.
Place resistors (1 Ω to 5 Ω typical) in series with GATE and
the main power MOSFET. These resistors aid in eliminating
any ringing on the drive voltages. Use a 100 nF capacitor
on the MODE pin if LLM is used in noisy environments.
5.
Ensure that RT pin resistor is Kelvin connected to AGND1
and not to a ground plane to avoid noise pickup.
The layout guidelines for the secondary side are as follows:
1.
Ground all the capacitors to their respective grounds. For
example, ground the SS2 capacitor to AGND2.
2.
Place resistors (1 Ω to 5 Ω) in series with SRx and the
synchronous MOSFET. These resistors aid in eliminating
any ringing on the drive voltages.
3.
The ground plane on the secondary side must be
connected to AGND2. The negative terminal of the output
voltage must be Kelvin connected to the AGND2 pin.
4.
Use the FB pin and the AGND2 pin to remotely differentially
sense the output voltage by connecting AGND2 to the
negative terminal of the output voltage using a 0 Ω resistor.


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