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ADP1071-1 Datasheet(Fiches technique) 21 Page - Analog Devices

Numéro de pièce ADP1071-1
Description  Isolated Synchronous Flyback Controller
Télécharger  27 Pages
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Fabricant  AD [Analog Devices]
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ADP1071-1 Datasheet(HTML) 21 Page - Analog Devices

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Data Sheet
Rev. B | Page 21 of 27
The ADP1071-2 employs a soft stop feature that brings the output
voltage gradually down to zero by using the SS2 pin as a reference.
During the soft stop procedure, the SS2 pin is discharged to zero by
a current sink of approximately 1.5 times the value during closed-
loop soft start.
When the voltage at EN drops below the EN threshold, the
SR secondary driver shuts off immediately, and the primary
GATE pulse width gradually decreases the duty cycle from the last
known condition to the minimum pulse width and down to zero,
causing the output voltage to decrease. The soft stop feature
prevents any reverse current when the controller is shut down.
When the output voltage decreases below the VDD2 UVLO
threshold, there is no transmission of the COMP signal to the
primary side. Therefore, the output voltage continues to decrease at
the rate at which the load current discharges the output capacitor.
When the load is at a minimum or at no load, the output voltage
does not discharge because any reduction in duty cycle or current
limit does not discharge the output voltage linearly.
During steady state, the FB pin is at 1.2 V. At this time, the SS2 pin
voltage is 1.4 V. Under abnormal situations, such as an overload
condition, the output voltage can dip severely. In such an event,
the current limit is at the maximum level, and the COMP pin
voltage is at its clamp level. If the two conditions of the COMP pin
voltage being clamped and VFB < (1.2 V − 100 mV) are satisfied,
the controller discharges the SS2 pin using a fast current sink
(200 µA) to make the SS2 pin equal to the FB pin. The controller
then attempts to perform a soft start from this precharged
condition, that is, from the last known value of the output
voltage. This process is how the OCP/feedback recovery feature
However, if at any time the voltage on the COMP pin is above
the maximum clamp voltage for a period greater than 1.5 ms,
the system enters hiccup mode.
During the soft start from precharge, the output voltage rises at
the same rate as determined by the capacitor on the SS2 pin.
The SS2 pin voltage determines the current limit during this
period. If, however, there is a detrimental fault in the power
stage that prevents the rise of the output voltage, VFB does not
track SS2 and when SS2 > (VFB + 100 mV), the COMP pin
voltage increases to the clamp level and the system again enters
the OCP/feedback recovery mode.
The ADP1071-1/ADP1071-2 offer a tracking feature. During
steady state, the FB pin is at 1.2 V. At this time, the SS2 pin
voltage is at 1.4 V. Using an external digital-to-analog converter
(DAC), the voltage on the SS2 pin can modulate the output
voltage. It is recommended that the SS2 pin voltage be changed
only after the VDD2 UVLO point is crossed, and control is
handed over to the secondary side, or else the handover process
does not occur smoothly, resulting in glitches in the output
The SS2 voltage must be brought down from 1.4 V to 1.2 V, and
it must be brought down even further to effect any change in the
output voltage. The rate at which the output tracks the SS2 pin
is dependent upon the overall system bandwidth.
For a remote (secondary side) system shutdown, an open-drain
general-purpose input/output (GPIO) of an external
microcontroller can be used to force the SS2 pin to 0 V.
This pull-down causes the ADP1071-1/ADP1071-2 to regulate
to 0 V, and the ADP1071-1/ADP1071-2 enter pulse skip mode
or output a minimum duty cycle because the SS2 pin offsets
because of the finite resistance of the GPIO.
When the VDD2 is charged from the output bus, this setup is
equivalent to a system shutdown because when VDD2 < VDD2
UVLO, the ADP1071-1/ADP1071-2 enter a special hiccup
mode of 200 ms, (instead of the standard 40 ms hiccup).
When VDD2 is powered using auxiliary winding, the system
regulates to the voltage proportional to the voltage on the SS2 pin
and eventually enters the special hiccup mode previously
mentioned, after the auxiliary rail decays below the VDD2
UVLO threshold.
Therefore, the SS2 pin can achieve output tracking as well as a
secondary side shutdown, also known as remote system reset, as
shown in Figure 21.

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