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ADP1071-1 Datasheet(Fiches technique) 20 Page - Analog Devices

Numéro de pièce ADP1071-1
Description  Isolated Synchronous Flyback Controller
Télécharger  27 Pages
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ADP1071-1 Datasheet(HTML) 20 Page - Analog Devices

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Data Sheet
Rev. B | Page 20 of 27
A clock signal can be applied to SYNC on the fly or prior to the
soft start sequence. A dithered clock can also be applied to
SYNC to reduce the peak electromagnetic interference (EMI)
noise in the converter output and switch node. The internal
clock is able to lock onto the dithered clock cycle by cycle.
It is recommended to connect the SYNC pin to AGND1 if this
feature is not used.
There is a synchronous rectifier driver on the secondary side for
driving the synchronous switch. VDD2 is the front end of the
LDO at VREG2. The 5 V internal LDO at VREG2 powers the
SR drivers and all internal circuits on the secondary side. The
recommended power supply range at VDD2 is from 6 V to 36 V.
However, at 36 V input to VDD2, the power dissipation in the
LDO can be significant. If VDD2 is less than 5 V, the LDO
operates in the dropout region, where VREG2 and the driver
output are less than 5 V. In this case, it is recommended to
supply VDD2 with an auxiliary power supply greater than 5 V.
VDD2 can be directly connected to the converter output or an
auxiliary power supply, by using a third winding of the main
transformer. For additional drive strength, SR can be fed into an
external MOSFET driver such as the ADP3624 or the ADP3654.
When the output voltage exceeds the OVP threshold of 1.36 V,
the controller immediately shuts off the drivers (GATE and SR)
on both the primary and secondary side. When the voltage at the
OVP drops below the OV hysteresis level, the controller resumes
switching in the next switching period with the primary drivers,
followed by the phasing in of SR. The OVP feature causes the
system to enter hiccup for 200 ms if the voltage on the OVP pin
exceeds 1.36 V for a sustained period of 200 µs.
To maximize efficiency and avoid cross conduction between the
primary and secondary sides, a fixed dead time between GATE
and SR is provided, as shown in Figure 20.
30ns FIXED
50ns FIXED
Figure 20. Gate to SR Dead Time
The ADP1071-1 has a power saving mode feature in which the
LLM threshold is programmable by connecting a resistor from
the MODE pin to AGND1. A current source flowing through
this resistor directly sets up the LLM threshold, which is compared
to the COMP voltage on the primary side. The SR driver is turned
off when the COMP voltage on the primary is below the LLM
threshold, and conduction current continues to flow through
the body diode of the SR MOSFET. However, the primary gate
driver continues to operate in full PWM mode. When the
COMP voltage moves above the LLM threshold, the controller
operates in forced CCM.
When the COMP voltage rises above the LLM threshold (that
is, the MODE pin voltage), the SR PWMs gradually increase (or
phase in) from the duty cycle at light load to the steady state
duty cycle at the SR phase in rate. The SR phase in rate moves
the SR edges every 1.5 ns per µs. Without the phase in sequence,
a dip in the output voltage can occur if the SR PWMs transition
from zero to full duty cycle instantaneously.
In a load dump situation, for example, when the load is stepped
from full load to light load, that is, from continuous conduction
mode (CCM) to discontinuous conduction mode (DCM) oper-
ation, the duty cycles of the SR PWMs gradually phase out at
the SR phase out rate, which has the same numerical value of
the SR phase in rate. The phase out sequence of the SR PWMs
prevents reverse current in the secondary side, and at the same
time, optimizes the dynamic performance of the output response.
Note that the level of COMP is still above the minimum COMP
clamp level at this point, and the ADP1071-1 outputs duty
cycles with minimum on time.
If the load is further reduced and the COMP pin voltage becomes
equal to the minimum COMP clamp level, the ADP1071-1 enters
pulse skip mode.
Note that when the system enters light load mode, the synchronous
rectifiers terminate at the falling edge of GATE, which prevents
termination at a negative current.
Use the following formula to set up the LLM threshold:
IPEAK_LLM is the peak primary current at the particular no load
CSGAIN = 12.5.
IMODE is the current flowing out of the MODE pin.
For full time CCM operation, connect MODE to AGND1.
The ADP1071-2 does not have an LLM and always operates in
forced CCM. Pulse skipping is not available in the ADP1071-2.

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