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ADP1071-1 Datasheet(Fiches technique) 18 Page - Analog Devices
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ADP1071-1 Datasheet(HTML) 18 Page - Analog Devices
/ 27 page
Rev. B | Page 18 of 27
OUTPUT VOLTAGE SENSING AND FEEDBACK
The output voltage of the converter is set by a resistive divider
to the FB pin. The resistive divider must be set in a manner
such that the voltage at the FB pin is 1.2 V in steady state. The
output voltage must be differentially sensed using the FB pin
and the AGND2 pin.
LOOP COMPENSATION AND STEADY STATE
The FB pin feeds into the negative terminal of a transconductance
amplifier (or g
amplifier) with a gain of approximately 250 µA/V.
The positive input terminal of the g
amplifier is connected to SS2,
which provides the reference setpoint voltage. The output of the
amplifier is connected to the COMP pin. The voltage on the
COMP pin is representative of the current peak limit required to
sustain regulation. This pin is continuously sampled, and the
signal is transmitted to the primary side, where it is compared
to the sensed primary current using a comparator. When the
comparator trips, it causes GATE to terminate.
Typically, an RC network in series is connected between the
COMP pin and AGND2 for compensation. A high frequency
pole in the form of a capacitor can also be added in parallel to the
The output of the g
amplifier is clamped to a minimum and max-
imum current of approximately +40 µA and −65 µA, respectively.
The COMP node is clamped to a lower and higher level of
approximately 0.7 V and 2.52 V, respectively. This is
representative of the CS range from 0 mV to 120 mV.
For a peak current mode controller with a duty cycle higher than
50%, slope compensation is necessary for a stable operation. To
set up an external compensation in the ADP1071-1/ADP1071-2,
connect the external R
resistor (see Figure 30) between CS
and the current sense resistor, R
, to set up the slope voltage
ramp for the control signal. It is important to sense the signal
differentially. See the Layout Guidelines section for more details.
An internal ramp current starts from 0 µA at the minimum
duty cycle (that is, the beginning of the switching period) and
increases linearly toward a maximum of 20 µA at the end of the
switching period. The slope of the voltage ramp is the ramp
current times R
is sized using the following equation:
k = 0.5 for nominal cases and k = 1 for deadbeat control.
is the desired output voltage.
L is the output inductor.
N1 and N2 are the primary and secondary turns of the transformer.
is the switching period.
INPUT/OUTPUT CURRENT-LIMIT PROTECTION
There is no direct current-limit sensing circuit in the secondary
side, but the output current limit is indirectly set by sensing the
input primary peak current cycle by cycle. A leading edge
blanking time is added after the rising edge of the GATE signal
to avoid picking up any unwanted noise or ringing at the CS pin
at the start of the switching period.
The input peak current limit is set by connecting a sense resistor,
, from the source of the main MOSFET to AGND1, and
the sensed voltage appears at the CS pin. To generate the slope-
comp ramp, insert the slope compensation resistor, R
between CS and R
The CS current limit, V
, is internally set to 120 mV.
Calculate the R
is the CS current limit.
is the primary peak current.
When the sensed input peak current is above the CS limit
threshold, the controller operates in the cycle by cycle constant
current limit mode for 1.5 ms. Then, the controller immediately
shuts down the primary and secondary drivers. The controller
then enters hiccup mode for the next 40 ms and restarts the soft
start sequence after this timeout period.
The slope ramp can affect the accuracy of the current-limit
threshold because the voltage drop across R
the inaccuracy of the peak current limit. For instance, if the
added slope ramp voltage is 20% of the current-limit threshold,
the actual input peak current limit can be off by as much as 20%
depending on where the peak current-limit threshold is tripped
during the on cycle. In the event of an output short circuit, the
controller treats this condition as an overcurrent event and
enters the 40 ms hiccup mode.
Under certain situations, the ADP1071-1/ADP1071-2 exit OCP
hiccup mode. In this condition, even though the COMP pin is
at the maximum clamp level, the device does not enter hiccup
mode. It is guaranteed that the PWMs are terminated whenever
the CS maximum threshold is reached. The conditions under
which this can occur are as follows.
Under certain conditions, the ADP1071-1/ADP1071-2 exit
OCP hiccup mode. In these conditions, the COMP pin is at the
maximum clamp level, but the device does not enter hiccup
mode. However, it is guaranteed that the PWMs are terminated
whenever the CS maximum threshold is reached. The condition
under which the ADP1071-1/ADP1071-2 skip entering hiccup
mode is when VDD2 is powered through an auxiliary winding,
and an output short circuit occurs that results in the FB pin
having a voltage that is less than 300 mV. This event is more
prominent at high temperatures (>85°C) and can be exacerbated at
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