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ADP1071-1 Datasheet(Fiches technique) 16 Page - Analog Devices
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ADP1071-1 Datasheet(HTML) 16 Page - Analog Devices
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Rev. B | Page 16 of 27
PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO
The voltage at the VREG1 pin powers the internal circuitry,
primary side iCouplers, housekeeping circuits, and the primary
MOSFET driver at the GATE pin.
In the ADP1071-1, power must be supplied to the VREG1 using
an external start-up circuit.
In the ADP1071-2, a high voltage LDO regulator is connected
to the VIN pin and has a regulated output of 8 V at VREG1.
In the ADP1071-2, to reduce power consumption in the LDO
for input voltages higher than approximately 30 V, an auxiliary
winding on the transformer of the active clamp forward
topology can be used to power VREG1. This auxiliary supply
voltage must be higher than the regulated output at VREG1 so
that the LDO shuts off during normal operation.
In both the ADP1071-1 and ADP1071-2, the recommended
auxiliary voltage is from 8.5 V to 12.5 V because an internal
14 V Zener diode is connected at VREG1.
SECONDARY SIDE SUPPLY AND LDO
Two pins on the secondary side are supply pins: VDD2 and
The secondary side is typically powered by the output rail of the
converter by connecting it to the VDD2 pin. The UVLO for the
secondary side is typically 3.55 V, at which the secondary side
starts up. For output voltages less than the secondary UVLO
voltage, a third winding is required to generate an auxiliary voltage
to power the secondary circuitry. The internal 5 V LDO regulator
at the VREG2 pin powers the MOSFET drivers, secondary side
Couplers, and housekeeping circuits. When VDD2 is less than
5 V, the LDO regulator operates in dropout mode.
For output voltages higher than 24 V, connecting the output
voltage directly to VDD2 can result in significant power
dissipation in the LDO. For instance, at 24 V and with the total
driver current at 10 mA, the power dissipated in the LDO is
0.19 W (10 mA × 19 V). It is recommended to power VDD2
with an auxiliary voltage in the 8 V to 12 V range.
The enable threshold at the EN pin is precision voltage
referenced at 1.2 V.
In the ADP1071-1, the soft start procedure commences
immediately when VIN is above the UVLO voltage (typically
4.5 V) and the voltage at the EN pin rises above 1.2 V.
In the ADP1071-2, the soft start procedure commences after a
small delay when VIN is above the UVLO voltage (typically
4.5 V) and the voltage at the EN pin rises above 1.2 V. This
delay comprises the time taken to charge the capacitor at the
VREG1 pin through the internal 8 V LDO. After the internal
biasing is finished, the soft start procedure initiates.
Connect a resistive divider between EN and VIN to set up the input
start-up voltage (see Figure 18). An internal current source at EN
allows the user to program the UVLO start-up voltage with a
desirable hysteresis. To calculate the start-up voltage with
hysteresis, use the superposition theorem or nodal analysis to
obtain the EN pin voltage, as follows:
is the EN pin voltage.
is the current source at the EN pin (1 µA for turn on and
4 µA for turn off).
The user can adjust the R
, and R
resistors such that
≥ 1.2 V and obtain the desired hysteresis.
An internal 1 µA pull-down current is always on, and the 3 µA
current is active only when the V
is below the EN threshold
and becomes inactive when V
is above the EN threshold.
In general, a higher input voltage requires a larger hysteresis. It
is recommended to keep a capacitor on the EN pin to AGND1
to provide a low impedance path that prevents any noise, which
toggles the EN pin when the input voltage hovers at the threshold.
Figure 18. Precision EN with Adjustable Hysteresis
When the EN pin is less than the threshold, the system enables
the soft stop procedure. SR takes up to a maximum of two
switching periods to terminate. See the Soft Start Procedure
section for more details.
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