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AD9176 Fiches technique(PDF) 5 Page - Analog Devices |
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AD9176 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 151 page Data Sheet AD9176 Rev. A | Page 5 of 151 DIGITAL SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = +25°C, which corresponds to TJ = 51°C. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DAC UPDATE RATE Minimum 2.91 GSPS Maximum1 16-bit resolution, with interpolation 12.6 GSPS 16-bit resolution, no interpolation 6.16 GSPS Adjusted2 16-bit resolution, with interpolation 3.08 GSPS 16-bit resolution, no interpolation 6.16 GSPS DAC PHASE-LOCKED LOOP (PLL) VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY RANGES VCO Output Divide by 1 8.74 12.42 GSPS VCO Output Divide by 2 4.37 6.21 GSPS VCO Output Divide by 3 2.91 4.14 GSPS PHASE FREQUENCY DETECT INPUT FREQUENCY RANGE 25 770 MHz DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN−) FREQUENCY RANGES PLL Off 2.91 12.6 GHz PLL On M divider set to divide by 1 25 770 MHz M divider set to divide by 2 50 1540 MHz M divider set to divide by 3 75 2310 MHz M divider set to divide by 4 100 3080 MHz 1 The maximum DAC update rate varies depending on the selected JESD204B mode and the lane rate for the given configuration used. The maximum DAC rate according to lane rate and voltage supply levels is listed in Table 3. 2 The adjusted DAC update rate is calculated as fDAC, divided by the minimum required interpolation factor for a given mode or the maximum channel data rate for a given mode. Different modes have different maximum DAC update rates, minimum interpolation factors, and maximum channel data rates, as shown in Table 13. MAXIMUM DAC SAMPLING RATE SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit MAXIMUM DAC UPDATE RATE SVDD1.0 = 1.0 V ± 5% Lane rate > 11 Gbps 11.67 GSPS Lane rate ≤ 11 Gbps 12.37 GSPS SVDD1.0 = 1.0 V ± 2.5% Lane rate > 11 Gbps 11.79 GSPS Lane rate ≤ 11 Gbps1 12.6 GSPS 1 If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of 12.42 GSPS, as listed in Table 2. |
Numéro de pièce similaire - AD9176_V01 |
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Description similaire - AD9176_V01 |
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