AD5770R datasheet(51/59 Pages) AD

No de pièce	AD5770R

Description	6-Channel, 14-Bit, Current Output DAC

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Fabricant	AD [Analog Devices]

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Data Sheet

AD5770R

Rev. 0 | Page 51 of 59

Address: 0x27, Reset: 0x00, Name: CH0_DAC_MSB

Channel 0 DAC Data

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:0] DAC_DATA0[13:6] (R/W )

Table 46. Bit Descriptions for CH0_DAC_MSB

Bits

Bit Name

Description

Reset

Access

[7:0]

DAC_DATA0[13:6]

Channel 0 DAC data. These bits are the DAC code loaded into the DAC register for IDAC0.

0x0

R/W

Address: 0x28, Reset: 0x00, Name: CH1_DAC_LSB

Channel 1 DAC Data

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:2] DAC_DATA1[5:0] (R/W)

[1:0] RESERVED

Table 47. Bit Descriptions for CH1_DAC_LSB

Bits

Bit Name

Description

Reset

Access

[7:2]

DAC_DATA1[5:0]

Channel 1 DAC data. These bits are the DAC code loaded into the DAC register for IDAC1.

0x0

R/W

[1:0]

Reserved

Reserved.

0x0

R

Address: 0x29, Reset: 0x00, Name: CH1_DAC_MSB

Channel 1 DAC Data

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:0] DAC_DATA1[13:6] (R/W )

Table 48. Bit Descriptions for CH1_DAC_MSB

Bits

Bit Name

Description

Reset

Access

[7:0]

DAC_DATA1[13:6]

Channel 1 DAC data. These bits are the DAC code loaded into the DAC register for IDAC1.

0x0

R/W

Address: 0x2A, Reset: 0x00, Name: CH2_DAC_LSB

Channel 2 DAC Data

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:2] DAC_DATA2[5:0] (R/W)

[1:0] RESERVED

Table 49. Bit Descriptions for CH2_DAC_LSB

Bits

Bit Name

Description

Reset

Access

[7:2]

DAC_DATA2[5:0]

Channel 2 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC2.

0x0

R/W

[1:0]

Reserved

Reserved.

0x0

R

Address: 0x2B, Reset: 0x00, Name: CH2_DAC_MSB

Channel 2 DAC Data

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:0] DAC_DATA2[13:6] (R/W )

Table 50. Bit Descriptions for CH2_DAC_MSB

Bits

Bit Name

Description

Reset

Access

[7:0]

DAC_DATA2[13:6]

Channel 2 DAC data. These bits are the DAC code loaded into the DAC register for IDAC2.

0x0

R/W

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