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AD4112 Fiches technique(PDF) 23 Page - Analog Devices |
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AD4112 Fiches technique(HTML) 23 Page - Analog Devices |
23 / 58 page Data Sheet AD4112 Rev. A | Page 23 of 58 CONFIGURATION OVERVIEW After power-on or reset, the AD4112 default configuration is as follows: • Channel configuration: Channel 0 is enabled, the VIN0 and VIN1 pair is selected as the input. Setup 0 is selected. • Setup configuration: the analog input buffers are disabled and the reference input buffers are also disabled. The REF± pins are selected as the reference source. Note that for this setup, the default channel does not operate correctly because the input buffers need to be enabled for a VIN input. • Filter configuration: the sinc5 + sinc1 filter is selected and the maximum output data rate of 31.25 kSPS is selected. • ADC mode: continuous conversion mode and the internal oscillator are enabled. The internal reference is disabled. • Interface mode: CRC and the data and status output are disabled. Note that only a few of the register setting options are shown. This list is only an example. For full register information, see the Register Details section. Figure 35 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: • Channel configuration (see Box A in Figure 35) • Setup configuration (see Box B in Figure 35) • ADC mode and interface mode configuration (see Box C in Figure 35) Channel Configuration The AD4112 has 16 independent channels and 8 independent setups. The user can select any of the input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configuration. This flexibility also allows per channel configuration when using differential inputs and single-ended inputs because each channel can have its own dedicated setup. Channel Registers The channel registers select which of the voltage or current inputs is used for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which are used to select which of the eight available setups to use for this channel. When the AD4112 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 15. If a channel is disabled, it is skipped by the sequencer. Details of the channel register for Channel 0 are shown in Table 12. ADC MODE AND INTERFACE MODE CONFIGURATION SELECT ADC OPERATING MODE, CLOCK SOURCE, ENABLE CRC, DATA AND STATUS, AND MORE SETUP CONFIGURATION 8 POSSIBLE ADC SETUPS SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE CHANNEL CONFIGURATION SELECT INPUT AND SETUP FOR EACH ADC CHANNEL A B C Figure 35. Suggested ADC Configuration Flow Table 12. Channel Register 0 Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x10 CH0 [15:8] CH_EN0 SETUP_SEL0 Reserved INPUT[9:8] 0x8001 RW [7:0] INPUT[7:0] |
Numéro de pièce similaire - AD4112 |
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Description similaire - AD4112 |
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