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AD4111 Fiches technique(PDF) 22 Page - Analog Devices |
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AD4111 Fiches technique(HTML) 22 Page - Analog Devices |
22 / 59 page AD4111 Data Sheet Rev. A | Page 22 of 59 AD4111 RESET After a power-up cycle and when the power supplies are stable, a device reset is required. In situations where interface synchro- nization is lost, a device reset is also required. A write operation of at least 64 serial clock cycles with DIN high returns the ADC to the default state by resetting the entire device, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high sets the digital interface to the default state and halts any serial interface operation. Table 10. Communications Register Bit Map Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x00 COMMS [7:0] WEN R/W RA 0x00 W Table 11. ID Register Bit Map Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x07 ID [15:8] ID[15:8] 0x30DX1 R [7:0] ID[7:0] 1 X means don’t care. |
Numéro de pièce similaire - AD4111 |
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Description similaire - AD4111 |
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