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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD4110-1 Fiches technique(PDF) 70 Page - Analog Devices |
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AD4110-1 Fiches technique(HTML) 70 Page - Analog Devices |
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70 / 74 page  AD4110-1 Data Sheet Rev. 0 | Page 70 of 74 Bits Bit Name Settings Description Reset Access [9:8] AIN_BUFF Analog input buffer configuration. 0x3 RW 00 Disable input buffer. 01 Enable negative input buffer only. 10 Enable positive input buffer only. 11 Full buffer enabled. 7 Reserved Reserved. 0x0 R 6 BIT_6 Set this bit to 1. 0x1 RW [5:4] REF_SEL Reference source select. If the internal voltage reference is selected, the REF_EN bit (Bit 15) in the ADC_MODE register (Address 0x1) must also be set. 0x0 RW 00 External voltage reference connected to REFIN(+)/REFIN(−) pins. 01 Reserved. 10 Internal 2.5 V reference. 11 AVDD5 and AGND. 3 CHAN_EN_3 Enable Channel 3 (low voltage channel): AIN2(LV) − AINCOM(LV). 0x0 RW 0 Disabled. 1 Enabled. 2 CHAN_EN_2 Enable Channel 2 (low voltage channel): AIN1(LV) − AINCOM(LV). 0x0 RW 0 Disabled. 1 Enabled. 1 CHAN_EN_1 Enable Channel 1 (low voltage channel): AIN1(LV) − AIN2(LV). 0x0 RW 0 Disabled. 1 Enabled. 0 CHAN_EN_0 Enable Channel 0 (high voltage channel): AIN(+) − AIN(−). Channel 0 is enabled automatically when Bits[3:0] = 00. 0x0 RW 0 Disabled. 1 Enabled. Data Register Address: 0x4, Reset: 0x000000, Name: Data The read-only data register contains the ADC conversion result. Reading the data register takes the RDY bit and the DOUT/RDY pin high. The ADC result can be read multiple times. However, after the RDY bit and the DOUT/RDY pin are brought high, it is not possible to determine whether another ADC result is imminent. The ADC does not write a new result to the data register if the data register is currently being read. Table 42. Bit Descriptions for the Data Register Bits Bit Name Settings Description Reset Access [23:0] Data ADC conversion result. If the DATA_STAT bit is set in the ADC_INTERFACE register, the contents of the ADC_STATUS register are appended to this register when it is read, making this a 32-bit register. If the WL16 bit is set in the ADC_INTERFACE register, this register is rounded to 16 bits. 0x0 R |
Numéro de pièce similaire - AD4110-1 |
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Description similaire - AD4110-1 |
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