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ADV7400AKSTZ-1101 Fiches technique(PDF) 9 Page - Analog Devices |
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ADV7400AKSTZ-1101 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 16 page ADV7400A Rev. A | Page 9 of 16 Pin No. Mnemonic Type Description 3 INT O Interrupt Pin. This pin can be programmed active low or active high. When SDP/CP status bits change, this pin triggers an interrupt. The set of events which triggers an interrupt can be modified via I2C registers. 4 HS/CS O Horizontal Synchronization/Composite Synchronization. HS is a horizontal synchronization output signal in SDP and CP modes. CS is a digital composite synchronization signal that can be selected while in CP mode. 99 VS O Vertical Synchronization. Vertical synchronization output signal in SDP and CP modes. 98 FIELD/DE O Field Synchronization/Data Enable. Field synchronization output signal in all interlaced video modes. This pin also can be enabled as a data enable signal in CP mode to allow direct connection to a HDMI/DVI Tx IC. 81, 19 SDA1, SDA2 I/O I2C Port Serial Data Input/Output Pin. SDA1 is the data line for the control port and SDA2 is the data line for the VBI readback port. 82, 16 SCLK1, SCLK2 I I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the control port, and SCLK2 is the clock line for the VBI data readback port. 80 ALSB I This pin selects the I2C address for the ADV7400A control and VBI readback ports. When set to a Logic 0, ALSB sets the address for a write to control port of 0x40 and the readback address for the VBI port of 0x21. When set to a Logic 1, ALSB sets the address for a write to the control port of 0x42 and the readback address for the VBI port of 0x23. 78 RESET I System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7400A circuitry. 36 LLC1 O Line-locked output clock for the pixel data output by the ADV7400A (the range is 13.5 MHz to 110 MHz for the ADV7400AKSTZ-110; 13.5 MHz to 80 MHz for the ADV7400AKSTZ-80). 38 XTAL I Input pin for 27 MHz crystal, or it can be overdriven by an external 3.3 V 27 MHz clock oscillator source to clock the ADV7400A. 37 XTAL1 O This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7400A. In crystal mode the crystal must be a fundamental crystal. 46 ELPF O The recommend external loop filter must be connected to this ELPF pin. 15 SFL/SYNC_OUT O SFL (Subcarrier Frequency Lock). This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. SYNC_OUT is the sliced sync output signal available only in CP mode. 64 REFOUT O Internal Voltage Reference Output. 65 CML O Common-Mode Level Pin for the Internal ADCs. 61, 62 CAPY1 to CAPY2 I ADC Capacitor Network. 68, 69 CAPC1 to CAPC2 I ADC Capacitor Network. 67 BIAS O External Bias Setting Pin. Connect the recommended resistor between this pin and ground. 86 HS_IN/CS_IN I Can be configured in CP mode to be either a digital HS input signal or a digital CS input signal, which are used to extract timing in 5-wire or 4-wire RGB mode. 85 VS_IN I VS Input Signal. Used in CP mode for 5-wire timing mode. 79 DE_IN I Data Enable Input Signal. Used in 24-bit digital input port mode, for example, 24-bit RGB data from a DVI Rx IC. 59 NC NC No Connect Pin. This pin can be tied to AGND or AVDD. 35 DCLK_IN I Clock Input Signal. Used in 24-bit digital input mode and also in digital CVBS input mode. 52 SOG I Sync On Green Input Pin. Used in embedded sync mode. 77 SOY I Sync On Luma Input Pin. Used in embedded sync mode. |
Numéro de pièce similaire - ADV7400AKSTZ-1101 |
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Description similaire - ADV7400AKSTZ-1101 |
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