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ADV7400AKSTZ-80 Fiches technique(PDF) 5 Page - Analog Devices

No de pièce ADV7400AKSTZ-80
Description  10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
Download  16 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADV7400AKSTZ-80 Fiches technique(HTML) 5 Page - Analog Devices

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ADV7400A
Rev. A | Page 5 of 16
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 3. Timing Characteristics1, ,2 3
Parameter
Symbol Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
27.0
MHz
Crystal Frequency Stability
±50
ppm
Horizontal Sync Input Frequency
14.8
110
kHz
LLC1 Frequency Range4
12.825
110
MHz
I2C® PORT
SCLK Frequency
400
kHz
SCLK Min Pulse Width High
t1
0.6
µs
SCLK Min Pulse Width Low
t2
1.3
µs
Hold Time (Start Condition)
t3
0.6
µs
Setup Time (Start Condition)
t4
0.6
µs
SDA Setup Time
t5
100
ns
SCLK and SDA Rise Time
t6
300
ns
SCLK and SDA Fall Time
t7
300
ns
Setup Time for Stop Condition
t8
0.6
µs
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio
t9:t10
45:55
55:45
% duty
cycle
DATA and CONTROL OUTPUTS
Data Output Transition Time (SDP)
t11
Negative clock edge to start of valid data
3.4
ns
Data Output Transition Time (SDP)
t12
End of valid data to negative clock edge
2.4
ns
Data Output Transition Time (CP)
t13
End of valid data to negative clock edge
1.1
ns
Data Output Transition Time (CP)
t14
Negative clock edge to start of valid edge
2.2
ns
Data Output Transition Time DDR (CP)5 t15
Positive clock edge to end of valid data
−2.7 + TLLC1/4
ns
Data Output Transition Time DDR (CP)5 t16
Start of valid data to positive clock edge
−1.3 + TLLC1/4
ns
Data Output Transition Time DDR (CP)5 t17
Negative clock edge to end of valid data
−2.1 + TLLC1/4
ns
Data Output Transition Time DDR (CP)5 t18
Start of valid data to negative clock edge
−0.9 + TLLC1/4
ns
DATA and CONTROL INPUTS
Input Setup Time
t19
HS_IN, VS_IN
9
ns
DE_IN, data inputs
2.2
ns
Input Hold Time
t20
HS_IN, VS_IN
7
ns
DE_IN, data inputs
1
ns
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX:
−40°C to +85°C.
3 Guaranteed by characterization.
4 Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80.
5 DDR timing specifications depend on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.


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