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ADV202-SD-EB Fiches technique(PDF) 8 Page - Analog Devices |
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ADV202-SD-EB Fiches technique(HTML) 8 Page - Analog Devices |
8 / 40 page ADV202 Rev. 0 | Page 8 of 40 DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter Description Min Typ Max Unit DREQPULSE1 DREQ Pulse Width 1 15 JCLK cycles2 t DREQ DACK Assert to Subsequent DREQ Delay 2.5 3.5 × JCLK + 7.5 ns JCLK cycles t WESU WE to DACK Setup 0 ns tSU Data to DACK Deassert Setup 2 ns tHD Data to DACK Deassert Hold 2 ns DACKLO DACK Assert Pulse Width 2 JCLK cycles DACKHI DACK Deassert Pulse Width 2 JCLK cycles t WEHD WE Hold after DACK Deassert 0 ns WFSRQ WE Assert to FSRQ Deassert (FIFO Full) 1.5 2.5 × JCLK + 7.5 ns JCLK cycles t DREQRTN DACK to DREQ Deassert (DR × PULS = 0) 2.5 3.5 × JCLK + 7.5 ns JCLK cycles 1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed. 2 For a definition of JCLK, see the PLL section. WE DACK DREQ HDATA 3 2 1 0 DREQPULSE tDREQ DACKHI DACKLO tWESU tSU tHD tWEHD Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000) WE DACK DREQ HDATA 0 1 2 tDREQRTN DACKHI DACKLO tWESU tSU tHD tWEHD Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) |
Numéro de pièce similaire - ADV202-SD-EB |
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Description similaire - ADV202-SD-EB |
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