RC5050
PRODUCT SPECIFICATION
2
Pin Assignments
Pin Definitions
Pin
Number
Pin
Name
Pin Function Description
1
CEXT
Oscillator Capacitor Connection. Connecting an external capacitor to this pin sets the
internal oscillator frequency. Layout of this pin is critical to system performance. See
Application Information for details.
2
ENABLE
Output Enable. Open collector/TTL input. Logic LOW will disable output. A 10K
Ω internal
pull-up resistor assures correct operation if pin is left unconnected.
3
PWRGD
Power Good Flag. Open collector output will be at logic HIGH under normal operation.
Logic LOW indicates output voltage is not within
±12% of nominal.
4
IFB
High Side Current Feedback. Pins 4 and 5 are used as the inputs for the current feedback
control loop and as the short circuit current sense points. Layout of these traces is critical
to system performance. See Application Information for details.
5
VFB
Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop and as
the low side current feedback input. Layout of this trace is critical to system performance.
See Application Information for details.
6
VCCA
Analog Vcc. Connect to system 5V supply and decouple to ground with 0.1
µF ceramic
capacitor.
7
VCCD
Digital Vcc. Connect to system 5V supply and decouple to ground with 4.7
µF tantalum
capacitor.
8
VID4
VID4 Input. A logic 1 on this open collector/TTL input will enable the VID3–VID0 inputs to
set the output from 2.1V to 3.5V, and a logic 0 on this pin will set the output from 1.3V to
2.05V, as shown in Table 1. Pullup resistors are internal to the controller.
9, 11
NC
No Internal Connection. Connection of these pins to system ground will improve the
thermal dissipation characteristics of the package.
10
GNDP
Power Ground. Return pin for high currents flowing in pins 12 and 13 (HIDRV and
VCCQP). Connect to low impedance ground.
12
HIDRV
FET Driver Output. Connect this pin to the gates of N-channel MOSFETs M1 and M2 in
Figure 1. The trace from this pin to the MOSFET gates should be < 0.5".
13
VCCQP
Power Vcc. This is the power supply for the FET driver. VCCQP must be connected to a
voltage of at least VCCA + VGS,ON (M1). See Application Information for details.
14
GNDD
Digital Ground. Return path for digital logic. This pin should be connected to system
ground to minimize ground loops.
15
GNDA
Analog Ground. Return path for low power analog circuitry. Connect to system ground to
minimize ground loops.
16
VREF
Reference Voltage Test Point. This pin provides access to the DAC output and should be
decoupled to ground using a 0.1
µF capacitor. No load should be connected.
17–20
VID3–
VID0
Voltage Identification (VID) Code Inputs. These open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 1. Pullup resistors are
internal to the controller.
1
2
3
4
5
6
8
7
VID0
VID1
VID2
VID3
VREF
GNDA
VCCQP
GNDD
20
19
18
17
16
15
13
9
12
10
11
14
CEXT
ENABLE
PWRGD
IFB
VFB
VCCA
VID4
VCCD
NC
HIDRV
GNDP
NC
65-5050-02
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