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74LVQ541TTR Fiches technique(PDF) 1 Page - STMicroelectronics |
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74LVQ541TTR Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 12 page 1/12 July 2004 s HIGH SPEED: tPD =5.8 ns (TYP.) at VCC = 3.3 V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C s LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 541 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ541 is a low voltage CMOS OCTAL BUS BUFFER with 3 STATE OUTPUTS NON INVERTED fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. The 3-STATE control gate operates as two input and such that if either G1 and G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the 74AC541 offers a pinout having inputs and outputs on opposite side of the package. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVQ541 OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LVQ541MTR TSSOP 74LVQ541TTR TSSOP SOP Rev. 2 |
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