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NUC200-VA2C Fiches technique(PDF) 60 Page - Nuvoton Technology Corporation |
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NUC200-VA2C Fiches technique(HTML) 60 Page - Nuvoton Technology Corporation |
60 / 107 page NUC100/120xxxDN Aug 31, 2015 Page 60 of 107 Rev 1.01 Clock Controller 6.3 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when Cortex ® -M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1. After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns off the external 4~24 MHz high speed crystal and internal 22.1184 MHz high speed oscillator to reduce the overall system power consumption. |
Numéro de pièce similaire - NUC200-VA2C |
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Description similaire - NUC200-VA2C |
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