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GPCE2064A-NnnV-C Fiches technique(PDF) 11 Page - Generalplus Technology Inc.

No de pièce GPCE2064A-NnnV-C
Description  16-bit Sound Controller with 32K X 16 ROM
Download  24 Pages
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Fabricant  GENERALPLUS [Generalplus Technology Inc.]
Site Internet  http://www.generalplus.com
Logo GENERALPLUS - Generalplus Technology Inc.

GPCE2064A-NnnV-C Fiches technique(HTML) 11 Page - Generalplus Technology Inc.

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GPCE2064A
© Generalplus Technology Inc.
Proprietary & Confidential
11
Jun 02, 2016
Version: 1.2
TimerA/CounterA -
“1” representing pass signal (not gating), and
“0” meaning timer deactivated. For instance, if Input 1=”1”, the
clock is depending on Input 2.
If Input 1=
”0”, the TimerA is
deactivated.
The EXT1/ETX2 is the external clock source 1 and
external clock source 2.
TMXSEL
Input 1
Input 2
0000
‘0’
‘0’
0001
‘1’
‘1’
0010
FRTC
EXT2
0011
FPLL
EXT2
0100
EXT2
64Hz
0101
EXT2
16Hz
0110
EXT2
2Hz
0111
EXT2
‘1’
1000
FRTC
64Hz
1001
FRTC
16Hz
1010
FRTC
2Hz
1011
FRTC
‘1’
TMXSEL
Input 1
Input 2
1100
FPLL
64Hz
1101
FPLL
16Hz
1110
FPLL
2Hz
1111
FPLL
‘1’
The following clock source A/B/C means clock source for Timer
A/B/C respectively.
Generally speaking, the clock source A and
C are fast clock sources and source B comes from RTC system
(32768Hz).
Therefore, clock source B can be utilized as a
precise counter for time counting, e.g., the 2Hz clock can be
used for real time counting.
6.9.1 IO PWM
One IO PWMs which duty is selected from 1/256 to 254/256.
Example the below figure is a 3/256-duration cycle.
The PWMO
waveform
is
made
by
selecting
a
pulse
width
through
Port_PWM_Ctrl.
As a result, each 256 cycles will generate a
pulse width defined in control port.
These PWM signals can be
applied for controlling the speed of motor or other devices.
Tpwmo
Tduty
PWMO
TimerA_Timeout
...
...
...
1
2
3
4
5
6
7
8
9
1
2
3
4
5
251
252
253
254
255
256
6.9.2 Timebase
Timebase,
generated
by 32768Hz
crystal
oscillator,
is
a
combination of frequency selection.
Furthermore, timebase
generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt
sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock
6.10 Sleep Mode, Wakeup, Halt Mode, and Watchdog
6.10.1 Sleep and wakeup modes
1)
Sleep: After power-on reset, IC starts running until a sleep
command is issued.
When a sleep command is
accepted, IC will turn the system clock (PLL) off.
After all, it enters sleep mode.
2)
Wakeup: CPU awaking from sleep mode requires a wakeup
signal to turn the system clock (PLL) on.
The
FIQ/IRQ signal makes CPU to complete the
wakeup process and initialization.
The CPU
wakeup source is given in the following table.
Wakeup Source
FIQ source
Timer A interrupt
Timer B interrupt
Timer C interrupt
SPI interrupt
EXT1/EXT2/KEY
RTC
6.10.2 Watchdog Reset
The GPCE2064A provides another important feature, watchdog
reset.
If the watchdog function is enabled, a reset signal is
generated to reset system when watchdog counter is overflow.
The purpose of watchdog is to monitor whether the system
operates normally.
Within a certain period, watchdog register
must be cleared.
If it is not cleared, CPU assumes the program
has been running in an abnormal condition.
As a result, the
CPU will reset the system to the initial state and start running the
program all over again.


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