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GPCE060A-NnnV-C Fiches technique(PDF) 10 Page - Generalplus Technology Inc. |
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GPCE060A-NnnV-C Fiches technique(HTML) 10 Page - Generalplus Technology Inc. |
10 / 26 page GPCE060A © Generalplus Technology Inc. Proprietary & Confidential 10 Oct. 01, 2013 Version: 1.4 Tapwmo Tduty APWMO TimerA_Timeout Generally speaking, the clock source A and C are fast clock sources and source B comes from RTC system (32768Hz). Therefore, clock source B can be utilized as a precise counter for time counting, e.g., the 2Hz clock can be used for real time counting. 6.8.1. Timebase Timebase, generated by 32768Hz, is a combination of frequency selections. The outputs of timebase block are named to TMB1 and TMB2. TMB1 is frequency for TimerA (Clock source B). The TMB1 and TMB2 are the sources for Interrupt (IRQ6). Furthermore, timebases generates additional 2Hz to 4096Hz interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC). TMB2 TMB1 128Hz 8Hz 256Hz 16Hz 512Hz 32Hz 1024Hz 64Hz Default: 128Hz Default: 8Hz 6.9. Sleep, Wakeup and Watchdog 6.9.1. Wakeup and sleep 1) Sleep: After power-on reset, IC starts running until a sleep command occurs. When a sleep command is accepted, IC will turn the system clock (PLL) off. After all, it enters sleep mode. 2) Wakeup: CPU waking up from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The IRQ signal makes CPU to complete the wakeup process and initialization. The key wakeup and interrupt sources (IRQ1 - IRQ6) can be used for wakeup sources. 6.9.2. Watchdog The purpose of watchdog is to monitor if the system operates normally. Within a certain period, watchdog must be cleared. If watchdog is not cleared, CPU assumes the program has been running in an abnormal condition. As a result, the CPU will reset the system to the initial state and start running the program all over again. The watchdog function can be removed by bonding option. In GPCE060A, the clear period is 0.75 seconds. If watchdog is cleared within each 0.75 seconds, the system will not be reset. To clear watchdog, simply write “0bxxxx xxxx xxxx xx01” to Port_Watchdog_Clear(W). The content written to Port_Watchdog_Clear (W) for watchdog clearance must be exactly the same as the one illustrated above (0bxxxx xxxx xxxx xx01). Other values given to the Port_Watchdog_Clear (W) for watchdog clearance may end up with system reset. The watchdog function remains enabled during standby mode if the 32768Hz is turned on. 6.10. ADC (Analog to Digital Converter) / DAC The GPCE060A has eight channels 10-bit ADC (Analog to Digital Converter). The function of an ADC is to convert analog signal to digital signal, e.g. a voltage level into a digital word. The eight channels of ADC can be seven channels of line-in from IOA [6:0] or one channel microphone (MIC) input through amplifier and AGC controller. The MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential MIC Inputs (MICN, MICP). Moreover, an external resistor can be applied to adjust microphone gain and time of AGC operating. The AD needs to select source of line-in before conversion. The ADC is able to choose the external or internal (=AVDD) top reference voltage. If constant voltage source is unavailable, GPCE060A offers a constant voltage 2.0V with 5.0mA driving ability with a capacitor connected. The GPCE060A has two 10-bit D/A with 2.0mA or 3.0mA driving current for audio outputs, DAC1 and DAC2. |
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