Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼

Delete All


Preview PDF Download HTML

NUC140-VD1C Datasheet(Fiches technique) 42 Page - Nuvoton Technology Corporation

Numéro de pièce NUC140-VD1C
Description  ARM Cortex™-M0 32-BIT MICROCONTROLLER
Télécharger  89 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet

NUC140-VD1C Datasheet(HTML) 42 Page - Nuvoton Technology Corporation

Zoom Inzoom in Zoom Outzoom out
 42 / 89 page
background image
™ NUC120 Data Sheet
Publication Release Date: Jan. 2, 2012
- 42 -
Revision V2.03
ator and Capture Timer (PWM)
m Density has 2 sets of PWM group supports total 4 sets of
independent PWM outputs, PWM0~PWM7, or as
4, PWM5) and (PWM6,
tors. NuMicro
™ NUC100/NUC120 Low Density
only sup
, PWM3) with 2 programmable dead-zone generators.
1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-
correspondin PWM period down cou t
aches zero.
gured as one-shot mode to produce only one PWM
rm continuously.
lementary PWM paired function; the
PWM0 timer and Dead-zone
WM pairs of (PWM2, PWM3), (PWM4, PWM5) and
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching zero. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM-
timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with PWM
Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set
as one-shot mode, the down counter will stop and generate one interrupt request when it reaches
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
PWM Gener
™ NUC100/NUC120 Mediu
PWM Generators which can be configured as 8
4 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM
PWM7) with 4 programmable dead-zone genera
port 1 set of PWM group supports total 2 sets of PWM Generators which can be
configured as 4 independent PWM outputs, PWM0~PWM3, or as 2 complementary PWM pairs,
0, PWM1) and (PWM2
Each PWM Generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1,
counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-
e generator. The 4 sets of PWM Generators provide eight independent PWM interrupt flags
ch are set by hardware when the
n er re
Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM
errupt. The PWM generators can be confi
cycle signal or auto-reload mode to output PWM wavefo
When PCR.DZEN01 is set, PWM0 and PWM1 perform comp
paired PWM period, duty and dead-time are determined by
generator 0. Similarly, the complementary P
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively.

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89 

Datasheet Download

Lien URL

Privacy Policy
AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicit   |   Contactez-nous   |   Politique de confidentialit   |   Echange de liens   |   Manufacturer List
All Rights Reserved©

Mirror Sites
English :  |   English :  |   Chinese :  |   German :  |   Japanese :
Russian :  |   Korean :  |   Spanish :  |   French :  |   Italian :
Portuguese :  |   Polish :  |   Vietnamese :