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NUC120-LD3E Fiches technique(PDF) 41 Page - Nuvoton Technology Corporation |
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NUC120-LD3E Fiches technique(HTML) 41 Page - Nuvoton Technology Corporation |
41 / 89 page NuMicro ™ NUC120 Data Sheet Publication Release Date: Jan. 2, 2012 - 41 - Revision V2.03 The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to features of the bus are: bus (no central master) Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and timer-out counter overflows. External pull-up are needed for high output Programmable clocks allow versatile rate control Supports 7-bit addressing mode I2C-bus controllers support multiple address recognition ( Four slave address with mask option) 5.6.2 Features the bus. The main Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer |
Numéro de pièce similaire - NUC120-LD3E |
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Description similaire - NUC120-LD3E |
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