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NUC130-YB3E Fiches technique(PDF) 21 Page - Nuvoton Technology Corporation |
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NUC130-YB3E Fiches technique(HTML) 21 Page - Nuvoton Technology Corporation |
21 / 89 page NuMicro ™ NUC120 Data Sheet 5 FUNCTIONAL DESCRIPTION 5.1 ARM ® Cortex™-M0 Core The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 5-1 shows the functional controller of processor. Cortex-M0 Processor Core Nested Vectored Interrupt Controller (NVIC) Breakpoint and Watchpoint Unit Debugger interface Bus Matrix Debug Access Port (DAP) Debug Cortex-M0 processor Cortex-M0 components Wakeup Interrupt Controller (WIC) Interrupts Serial Wire or JTAG debug port AHB-Lite interface Figure 5-1 Functional Controller Diagram The implemented device provides: sor that features: et SysTick timer ts little-endian data accesses dling bandoned and ption model. This is the ARMv6-M, A low gate count proces The ARMv6-M Thumb® instruction s Thumb-2 technology ARMv6-M compliant 24-bit A 32-bit hardware multiplier The system interface suppor The ability to have deterministic, fixed-latency, interrupt han Load/store-multiples and multicycle-multiplies that can be a restarted to facilitate rapid interrupt handling C Application Binary Interface compliant exce C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers Publication Release Date: Jan. 2, 2012 - 21 - Revision V2.03 |
Numéro de pièce similaire - NUC130-YB3E |
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