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NUC100-RD1E Fiches technique(PDF) 31 Page - Nuvoton Technology Corporation |
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NUC100-RD1E Fiches technique(HTML) 31 Page - Nuvoton Technology Corporation |
31 / 89 page NuMicro ™ NUC120 Data Sheet Publication Release Date: Jan. 2, 2012 - 31 - Revision V2.03 5.2.6.2 Vector Table When any the processor will automatically fetch the starting address of the interrupt serv (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x0000 vector table tialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the o tries v ciated with exception handler entry as illustrated in previo interrupts is accepted, ice routine 0000. The contains the ini rder of en in the ector table asso us section. Ve Table Wo ffset ctor rd O Description 0 S he M ck P_main – T ain sta pointer Vector Num E try P usi umber ber xception En ointer ng that Vector N Table 5-4 V ab 5.2.6.3 NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set- Enable or Interrupt Clear-En er s use a write-1-to-enable and write- 1-to-clear policy, both regis g nabled state of the corresponding interrupts. When interrup ed t cause the interrupt to become Pending, however, the inter t I upt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of t NVIC interrupts can be pend ded a y pair of registers to those used to enable/disable the interru d the Se res tively. The registers te-1 b rs rea back the current te of the c nterrupts. The Clear-Pending Regi as no effect on the execut status of an A . NVIC interrupts are prioritized by updating an 8-bi gister (each register sup g four interrupts). The general registers associated with the NVIC are m a block of memory in the System Control Space and w ribed xt ector T le Format Operation Description able regist bit-field. The register ters readin t is disabl back the , interrup current e assertion will an rupt will no activate. f an interr he associated interrupt. ed/un-pen using complementar pts, name use a wri t-Pe -to-ena nding Register and Clear-Pending Register le and write-1-to-clear policy, both registe pec ding ster h pended sta ion orresponding i ctive interrupt t field within a 32-bit re portin all accessible fro ill be desc in ne section. |
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