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NUC130-VC1E Fiches technique(PDF) 37 Page - Nuvoton Technology Corporation |
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NUC130-VC1E Fiches technique(HTML) 37 Page - Nuvoton Technology Corporation |
37 / 89 page NuMicro ™ NUC120 Data Sheet Publication Release Date: Jan. 2, 2012 - 37 - Revision V2.03 utput e multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with where Fin is input clock frequency to the clock divider. EN (FRQDIV[4]), the chained counter starts to count. When write 0 to ntinuously runs till divided clock reaches low 5.3.6 Frequency Divider O This device is equipped a power-of-2 frequency divider which is composed by16 chained divide- by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to on the frequency from Fin/2 1 to F in/2 16 The output formula is F out = Fin/2 (N+1), where Fin is the input clock frequency, Fout is the clock divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]). When write 1 to DIVIDER_ DIVIDER_EN (FRQDIV[4]), the chained counter co state and stay in low state. Figure 5-7 Clock Source of Frequency Divider Figure 5-8 Block Diagram of Frequency Divider |
Numéro de pièce similaire - NUC130-VC1E |
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Description similaire - NUC130-VC1E |
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