Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

NUC130-LD3N Datasheet(Fiches technique) 41 Page - Nuvoton Technology Corporation

Numéro de pièce NUC130-LD3N
Description  ARM Cortex™-M0 32-BIT MICROCONTROLLER
Télécharger  89 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC130-LD3N Datasheet(HTML) 41 Page - Nuvoton Technology Corporation

Back Button NUC130-LD3N Datenblatt HTML 37Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 38Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 39Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 40Page - Nuvoton Technology Corporation NUC130-LD3N Datasheet HTML 41Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 42Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 43Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 44Page - Nuvoton Technology Corporation NUC130-LD3N Datenblatt HTML 45Page - Nuvoton Technology Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 89 page
background image
NuMicro
™ NUC120 Data Sheet
Publication Release Date: Jan. 2, 2012
- 41 -
Revision V2.03
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
features of the bus are:
bus (no central master)
Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
External pull-up are needed for high output
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
I2C-bus controllers support multiple address recognition ( Four slave address with
mask option)
5.6.2
Features
the bus. The main
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89 


Datasheet Download

Go To PDF Page


Lien URL



Privacy Policy
ALLDATASHEET.FR
AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicit   |   Contactez-nous   |   Politique de confidentialit   |   Echange de liens   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn